Clik here to view.
Show slack per node in timing report soc encounter 8.1
Hello,I have made a design, and after place&routing I want to study the timing report of the paths. This report I make trought the 'report_timing' command.With the -format, you can specify what...
View ArticleClik here to view.
IMC Merging Issue of diferent test case fro the same DUT.
Dear All,I'm trying to merge the coverage report of different test case of the same DUT but im getting an error saying. Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */...
View ArticleClik here to view.
help needed for irun error: can't open include file
Hi, I'm trying to compile my UVM testbench which is having some package files. At the time of compiling common_pkg.sv file which is one my packages the tool encountering ERROR showing "cannot open...
View ArticleClik here to view.
IVB not supporting additional port definations for systemverilog UVC creation
I am trying build UVC using IVB but IVB not showing Port definations dialog for Systemverilog-UVM where as it is showing it for UVM-e.Please help me to declare additional ports in IVB.
View ArticleClik here to view.
help with reflection
Hi allI am looking for a way to get all the local variables within a specific method.i didn't find an API function in rf_method struct that do such operation.i will happy if some one can show me how...
View ArticleClik here to view.
IDLE cycles between READ/WRITE transactions in the OCP eVC
Hi,I have an Verification environment with and OCP MASTER eVC connected to a OCP complaint Slave (RTL). We are trying out simulate multiple read/write transactions using the OCP eVC api methods write()...
View ArticleClik here to view.
how to update(backdoor) a register in rgm by address which have read only...
hi, i have few register in RGM which have only read access with sequential addresses. i can update the register(backdoor update) by writing the rgm pointer and register pointer and write function. but...
View ArticleClik here to view.
Creating e Wrapper for system verilog code
Hi all, I am try to creating eRM Wrapper for sv Environment. In that environment systemverilog tasks/function which is called from specman e methods. I have better knowledge in both Verification...
View ArticleClik here to view.
Inserting electrical to real connect modules automatically
This is based on the article in EE times http://www.eetimes.com/design/eda-design/4229801/Assertion-based-verification-in-mixed-signal-design vy 2 Cadence authors. Another post similar to this used a...
View ArticleClik here to view.
UVM_REG backdoor access
Hi , I am trying to implement register backdoor access with user defined register backdoor by extending uvm_reg_backdoor. class peri_reg_backdoor extends uvm_reg_backdoor...
View ArticleClik here to view.
Command Line argument for Simulate systemverilog DPI using ncverilog?
Hi all, i am getting stuck on simulating systemverilog code in cadence... DPI related systemverilog code is running under some other tool I need to run that code in cadence. I compile...
View ArticleClik here to view.
IFV assertion failure
While running an IFV assertion check, the trace and trigger are showing the status "Pass" whereas the result is shown as "Fail". Please tell me where the issue could be?
View ArticleClik here to view.
i am not getting rc timing delay values
hi, can any one help me to find the problem in my project.i am doing asic implementation of reed solomon encoder, in that while doing rc timing extraction i am not getting the timing delay value...can...
View ArticleClik here to view.
Specman error while running ENET VIP
Hi,I am getting the following specman related error. Modified the $PATH variable accordingly but of no use.Any ideas from anyone?Thanks,Naveen Here is the run.log...
View ArticleClik here to view.
Slow simulation caused by Assertions
I am using -profile to investigate why my simulation is so slow, and I found the warning: ncsim: *W,FLSTRTthe explanation of it is: The assertion is spending a significant amount of time starting new...
View ArticleClik here to view.
what does dont_use and dont_touch attributes mean
Hi I am new to standard cell, during reading the .lib report i found out there is dont_use and dont_touch on some cell.can any one let me know what do they mean thanks
View ArticleClik here to view.
Calling a parameter of a module in TCL
HIHow do i call/access the parameter which is defined inside a verilog module and then modify the values of the parameter so that the module behaves differently each time I run it.I am trying to...
View ArticleClik here to view.
Multi-Language ml_uvm for e_sv
Hi, for Initial Stage I just create Dummy Wrapper in UVM-SV for Checking purpose...Below is my Dummy file test.sv This file contain - sequence_item,driver,monitor,environement,top_tb,dut and...
View ArticleClik here to view.
problem with e linting with hal
Hi allI am using HAL for e linting and facing a problem with filtering source file for linting.I am using the a design_info.txt file method to filter files that i don't want to lint.however, this...
View ArticleClik here to view.
need help in formal verification with IEV tool
Hi Iam using IFV 12.20.007.Iam trying to pass constraint for a design,What is the procedure to give give constraint such if statement. Ex: i have condition to be satisfied iam using if statement for...
View Article