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View ArticleIMC Exclusion Problem
Hey all, I am using IMC for my coverage .The problem is the tool automaticaly excludes some block coverage or expressions from the coverage.It shows "Exclusion Rule type : simulation time".Can someone...
View ArticleVCS to IRUN Conversion Error, UVM-1.1 System Verilog
Hi, I am using INCISIV 11.1 to compile a project which works perfectly on VCS, However I get the following errors on cadence using the irun command .ncvlog: *E, CLSSLV Class reference illegal in this...
View Articlencsim: *F,INTERR: INTERNAL ERROR
Hi, Test : DRAM write and read up to 2GB . Simulation fails with the following error. Can anbody please help me out?ncsim(64): 06.20-p001: (c) Copyright 1995-2007 Cadence Design Systems, Inc.ncsim:...
View ArticleWhy do I get an error when I try to generate (any) system Verilog module?
If I try to make a new cell view of type system verilog from the library manager GUI I systematically get this error (the content of the module does not matter):F,AMSASV: The -ams and -sv options...
View ArticleIs it possible to make a system verilog module from the library manager GUI?
If I try to make a new cell view of type system verilog from the library manager GUI I systematically get this error (the content of the module does not matter):F,AMSASV: The -ams and -sv options...
View ArticleFailure of liveness property
Hi everybodyI'm trying to verify the following property:-- psl assert_p1: assert always ( (CS = st_idle) -> next eventually! ((CS = st_get_ack) or (CS = st_set_ack)) );The section "Waveforms for...
View Articlere : parameterized sequences & property blocks in simvision
HI, I have a strange problem with my simvision (version 11.10.-s66) that i have written 2 assertions 1) with parameterized sequnces and property 2) normal assertion for some logic...
View ArticleSVA library in Cadence INCISIV
Hi,I am migrating my project from Synopsys VCS to Cadence INCISIV. My project uses SVA library Cadence's library ial can not be used in this case. I get the following error when I compile the SVA...
View ArticleEngineering Fix
Hi I have been given an Engineering fix for a problem in formal tool. The IT suppor has installed it but I am not sure how to use it.Usually the tool is used by seting SOCV_KIT_HOME and sourcing...
View ArticleRetrieve Flat Net Wire Properties using TCL
Using the script example in section 3.2.20 of the OrCAD Capture TCL/TK Extensions Application Notes I was able to pull the net names. To get the other information I need (user properties, port...
View ArticleBidirectional has() and count() List Pseudo-Methods
Hi.As of the 11.1 release, the list.has() and list.count() list pseudo-methods can be treated as bidirectional constraint operators.In 11.1, list.has() and list.count() are solved unidirectionally by...
View ArticleIssue in merging two coverage runs with different checksums in IMC.
Hi all, I am trying to merge two different coverage runs with different checksum. It is not getting merged. I am getting messages like below. Block coverage not merged - Checksum differs....
View ArticleUVM_REG backdoor access
Hi , I am trying to implement register backdoor access with user defined register backdoor by extending uvm_reg_backdoor. class peri_reg_backdoor extends uvm_reg_backdoor...
View ArticleTCL based assertion for connectivity check
Hi, I am using ncsim and i wish to check connectivity between two nets in RTL/netlist using tcl. I remember there being someway where using tcl input file i could specify two nets which could be tested...
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