SimVision - Source browser doesn't opens the source code
Hi,The source browser tab doesn't display the source code of the highlighted design unit, while the source code file can be opened manually from the file menu. As I dug into the problem, I realized...
View ArticleCoverage results over the time (RTL)
Is it possible to track the coverage results over the time? For bug detection, it is well accepted that the rate at which bug are detected approximates an exponential decay. That is at beggining is...
View ArticleToggle, block, statement coverage... what else?
Incisive allows to measure toggle, block and statement coverage at RT level. Is it possible to use other coverage metrics for RTL descriptions? Does Incisive provide a fault injection feature?
View Articlencsim -out directive
Hi,I created a sub-directory inside the main directory where I am invoking Incisive to dump all the files generated using "-out" argument. In my design, I need to pick values from a certain file from...
View ArticleUniPro eVC integration
Hi,I'd like to integrate the CDN UniPro eVC to a verification component, that will be reused multiple times. I noticed that each layer in the UniPro stack communicates upwards and downward via method...
View Articlespecman clock
Hii need to use specman clock for the simulation in standalone mode instead of DUT clock. I read about si_util_time_mgr in a cadence...
View ArticleWarning in Toggle coverage exclusion
Hi ,I am getting the following warning when trying to exclude toggle coverage. ncelab: *W,PSEFDM: The pattern "sig_1" specified on line 7 of file "toggle_exclude.cf" did not result in exclusion of any...
View ArticleATPG for RTL
Does Cadence provide any ATPG for RTL descriptions? The goal should be to maximize some coverage metrics (e.g., toggle, block).
View ArticleCadence lint HAL tool
CG cell is not detected as gated clock, can u help me?i hv tried with below setting, but it didn't work.... params GTDCLK {identify_clock_gating_cell="no"}
View ArticleFSM coverage (RTL from CtoS)
I am trying to measuring FSM coverage of RTL code that tis generated with CtoS and co-simulated with its original TLM testbench (CtoS generates some wrappers for doing that). I am passing -COVFILE...
View Articlencelab ncutilities E,BUILDF
Hi all, Switching from release 10 to 12.2, I've found some problem with testbench which uses nc utilities. ncelab (version 12.2) with option "-update" exit with :...
View ArticleIFV Dead code check fail
In Formal properyty checking deadcode assertions and property getting failed.What is the meaning of these getting failed.How we can pass them.How to debug this
View Articlehow to reduce explored
Hi, Iam using IFV for formal property checking and i have some of the assertions/Property explored.How to make them either pass/fail. ThanksBharath
View ArticleGate Level Sim - SDF annotation debug
Hi, I am trying to annotate an SDF to my gate level synthesis netlist and I am seeing some strange behaviour. When I annotate using just the netlist, cell_lib and sdf , everything works fine. However,...
View Articlerun IFV Xcheck property
Hi Iam doing XCheck property checking.Now instead of running all the properties,I want to run only one XCheck property in IFV . How to prove single XCheck assertion.
View Articleuninitialized state elements
Hi,I have some of the stateelements uninitialized in my design.What could be the reason they are uninitialized.What will be the problems we will be having if we have uninitialized state elements. want...
View ArticleDIVA LVS Problem After Installing Assura
Hi, I'm a beginner and i'm trying to explain my problem as best i can. I use IC615 and Assura 41. After installing and putting Assura into my system (set environment variable ASSURAHOME) diva does not...
View ArticleCreate/Import Verilog-AMS Cell View
I have a problem with CADENCE, importing or creating a VERILOG-AMS file.I have to import a device model which has been developed in Verilog-AMS (I have a file with ".vams" extension). In the following,...
View ArticleHow to make eManager run in "parallel"
Hi,is there any why to configure eManager to work in parallel.to say,i want eManager to take all test for given Vsif and to be able to run them on a predefine (by user) number of stations (LSF -...
View ArticleAdding automatic assertions in IFV?
I've used the assertion -add -automatic command.But this doesn't add any assertions, but gives a warning saying: Session does not have any assertion.It runs user-defined assertions. Also, when the...
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