I am trying build UVC using IVB but IVB not showing Port definations dialog for Systemverilog-UVM where as it is showing it for UVM-e.
Please help me to declare additional ports in IVB.
↧
Channel:
Cadence Functional Verification Forum
X
Are you the publisher?
Claim or
contact us
about this channel.
X
0
Channel Details:
- Title: Cadence Functional Verification Forum
- Channel Number: 3711457
- Language: English
- Registered On: July 11, 2012, 10:00 pm
- Number of Articles: 1074
- Latest Snapshot: December 21, 2024, 9:52 pm
- RSS URL: http://feeds.feedburner.com/cadence/community/forums/30
- Publisher: https://community.cadence.com/cadence_technology_forums/f/functional-verification
- Description:
- Catalog: //kitthoge4.rssing.com/catalog.php?indx=3711457
© 2025 //www.rssing.com