Hi,
for Initial Stage I just create Dummy Wrapper in UVM-SV for Checking purpose...
Below is my Dummy file test.sv
This file contain - sequence_item,driver,monitor,environement,top_tb,dut and interface...
*** => important things are in Bold letter...
`include "uvm_macros.svh"
interface dut_if;
logic clk;
logic [7:0] addr;
logic [7:0] data;
endinterface
module dut(dut_if m_dut_if);
import uvm_pkg::*;
always@(posedge m_dut_if.clk)
begin
`uvm_info("", $sformatf("POSEDGE: DUT received addr=%d, data=%d",m_dut_if.addr,m_dut_if.data),UVM_MEDIUM)
end
always@(negedge m_dut_if.clk)
begin
`uvm_info("", $sformatf("NEGEDGE: DUT received addr=%d, data=%d",m_dut_if.addr,m_dut_if.data),UVM_MEDIUM)
end
endmodule
package hello_pkg;
import uvm_pkg::*;
class hello_sequence_item extends uvm_sequence_item;
`uvm_object_utils(hello_sequence_item)
rand int addr;
rand int data;
constraint c_addr { addr >= 0; addr < 256; }
constraint c_data { data >= 0; data < 256; }
function new (string name = "");
super.new(name);
endfunction
function string convert2string;
return $sformatf("addr=%0d, data=%0d",addr,data);
endfunction
function void do_copy(uvm_object rhs);
hello_sequence_item tx;
$cast(tx, rhs);
addr = tx.addr;
data = tx.data;
endfunction
function bit do_compare(uvm_object rhs, uvm_comparer comparer);
hello_sequence_item tx;
bit status = 1;
$cast(tx, rhs);
status &= (addr == tx.addr);
status &= (data == tx.data);
return status;
endfunction
endclass: hello_sequence_item
typedef uvm_sequencer #(hello_sequence_item) hello_sequencer;
class hello_sequence extends uvm_sequence #(hello_sequence_item);
`uvm_object_utils(hello_sequence)
hello_sequence_item item_h;
function new (string name = "");
super.new(name);
endfunction
task body;
if (starting_phase != null)
starting_phase.raise_objection(this);
repeat(8)
begin
item_h = hello_sequence_item::type_id::create("item_h");
start_item(item_h);
if( !item_h.randomize() )
`uvm_error("", "Randomize failed")
finish_item(item_h);
end
if (starting_phase != null)
starting_phase.drop_objection(this);
endtask: body
endclass: hello_sequence
class hello_driver extends uvm_driver #(hello_sequence_item);
`uvm_component_utils(hello_driver)
virtual dut_if m_dut_if;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
if( !uvm_config_db #(virtual dut_if)::get(this, "", "dut_if", m_dut_if))
//`uvm_error("CONFIG", "uvm_config_db::get failed")
`uvm_fatal("CONFIG",{"config must be set for : ",get_full_name(),".m_dut_if"});
endfunction
task run_phase(uvm_phase phase);
forever
begin
seq_item_port.get_next_item(req);
// Wiggle pins of DUT
@(posedge m_dut_if.clk);
m_dut_if.addr = req.addr;
m_dut_if.data = req.data;
`uvm_info("", $sformatf("DRIVER POSEDGE addr=%d, data=%d",m_dut_if.addr,m_dut_if.data),UVM_MEDIUM)
@(negedge m_dut_if.clk);
m_dut_if.addr = req.addr;
m_dut_if.data = req.data;
`uvm_info("", $sformatf("DRIVER NEGEDGE addr=%d, data=%d",m_dut_if.addr,m_dut_if.data),UVM_MEDIUM)
seq_item_port.item_done();
end
endtask
endclass: hello_driver
class hello_monitor extends uvm_monitor;
`uvm_component_utils(hello_monitor)
int mon_addr;
int mon_data;
virtual dut_if m_dut_if;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
if( !uvm_config_db #(virtual dut_if)::get(this, "", "dut_if", m_dut_if))
`uvm_error("", "uvm_config_db::get failed")
endfunction
task run_phase(uvm_phase phase);
forever
begin
@(negedge m_dut_if.clk);
mon_addr=m_dut_if.addr;
mon_data=m_dut_if.data;
`uvm_info("", $sformatf("MONITOR NEGEDGE addr=%d, data=%d",mon_addr,mon_data),UVM_MEDIUM)
@(posedge m_dut_if.clk);
mon_addr=m_dut_if.addr;
mon_data=m_dut_if.data;
`uvm_info("", $sformatf("MONITOR POSEDGE addr=%d, data=%d",mon_addr,mon_data),UVM_MEDIUM)
m();
end
endtask
task m();
`uvm_info(get_type_name(), "I am here", UVM_MEDIUM)
endtask
endclass: hello_monitor
class hello_env extends uvm_env;
`uvm_component_utils(hello_env)
hello_driver driver;
hello_sequencer sequencer;
hello_monitor monitor;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
sequencer = hello_sequencer::type_id::create("sequencer",this);
driver = hello_driver::type_id::create("driver",this);
monitor = hello_monitor::type_id::create("monitor",this);
endfunction
function void connect_phase(uvm_phase phase);
driver.seq_item_port.connect( sequencer.seq_item_export );
endfunction
endclass: hello_env
class hello_test extends uvm_test;
`uvm_component_utils(hello_test)
hello_env my_env;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
my_env=hello_env::type_id::create("my_env",this);
endfunction
task run_phase(uvm_phase phase);
hello_sequence seq;
seq=hello_sequence::type_id::create("seq");
`uvm_info("", "Hello World_0", UVM_MEDIUM)
if( !seq.randomize() )
`uvm_error("", "Randomize failed")
seq.starting_phase = phase;
seq.start(my_env.sequencer);
`uvm_info("", "Hello World", UVM_MEDIUM)
endtask
endclass: hello_test
endpackage: hello_pkg
module top;
import uvm_pkg::*;
import ml_uvm::*; => ///For multi-Language interaction i am just import multi-language
import hello_pkg::*;
dut_if dut_if1 ();
dut dut_m ( .m_dut_if(dut_if1) );
initial
begin
dut_if1.clk = 0;
forever #5 dut_if1.clk = ~dut_if1.clk;
end
initial
begin
uvm_config_db #(virtual dut_if)::set(null, "*", "dut_if", dut_if1);
//uvm_top.finish_on_completion = 1;
run_test("hello_test");
end
endmodule
if I run above test.sv in cadence simualtor with following command #! /bin/sh -f
IUS_HOME=`ncroot`
irun -access rw \
-uvmhome ${IUS_HOME}/tools/uvm-1.1 \
-uvmtop sv:hello_env \
test.sv
I am getting below error,
UVM_FATAL test.sv(98) @ 0: hello_env.driver [CONFIG] config must be set for : hello_env.driver.m_dut_if
--- UVM Report catcher Summary ---
anybody Guide me to Resolve this issue...
Thanks,
selvavinayakam.na