Inserting electrical to real connect modules automatically

This is based on the article in EE times http://www.eetimes.com/design/eda-design/4229801/Assertion-based-verification-in-mixed-signal-design vy 2 Cadence  authors. Another post similar to this used a VAMS test bench it seems http://www.cadence.com/community/forums/T/22576.aspx.

I am trying to implement this simple test bench in the following manner:

  // Module top.sv

module top;
var real r, xr, wr;
assign xr = 3.14;

ams_electrical_src e_s1(r);

// causes insertion of Electrical2Real connection module
ams_electrical_dst e_d1(xr);

// causes insertion of Real2Electrical connection module
ams_wreal_src w_s1(wr);

// Coercion of SystemVerilog real variable to wreal

endmodule

// Module ams_electrical_src.vams
`timescale 10ns / 10ps
`include "disciplines.vams"
module ams_electrical_src(e);
  output e; electrical e;
  analog V(e) <+ 5.0;
endmodule

 //Module ams_electrical_dst.vams
`timescale 10ns / 10ps
//`include "disciplines.vams"

module ams_electrical_dst(e);
  input e; electrical e;
  initial #10 $display("%M: %f", V(e));
endmodule

// Module ams_wreal_src.vams
`timescale 10ns / 10ps
//`include "disciplines.vams"
module ams_wreal_src(w);
  output w; wreal w;
  assign w = 2.5;
endmodule

 Compile :

irun -timescale 1ns/1ps -discipline logic -ieinfo ieinfo.txt top.sv ams_electrical_src.vams ams_electrical_dst.vams ams_wreal_src.vams

Errors:

 Discipline resolution Pass...
ams_electrical_src e_s1(r);
                        |
ncelab: *E,CUVNCM (./top.sv,7|24): No connection module found:Need a wreal input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance top.e_s1.
ams_electrical_dst e_d1(xr);
                         |
ncelab: *E,CUVNCM (./top.sv,10|25): No connection module found:Need a wreal input port of discrete discipline logic, and an output port of continuous discipline electrical, at instance top.e_d1.
irun: *E,ELBERR: Error during elaboration (status 1), exiting.

Tool: IUS 10.029

Questions:

1. Does IUS 10.029 support automatic insertion of connect modules as mentioned in the EE times article above?

2. I tried explicitly to use -setdiscipline to set the net "e" to electrical but to no avail

Any pointers/help to resolve this would be highly appreciated. I am planning on using SVA's in the test bench to monitor electrical signals from the analog blocks and hence the help would be highly appreciated. Thx