How to link static library(.a) use xrun?
I have a static library file (libstatic.a) compiled from C language. Now I want to use some function in this library. But I don't know how to link this file using xrun. It seems that -sv_lib can only...
View ArticleRegular expression for keeping
I have registers defined in vr_ad (with reg_def and reg_fld) and I have a macro that makes me possible to make writes to it, even to fields, e.g.:wr_reg REG1 keeping {.fld1== val1}I would like to have...
View ArticlePassing variables between structs and sequences
Hi all,I'm Trying to create an effective "end of test" condition where I generate packets in a designed unit and send them to a sequence.I'm interested that after a X amount of packets the sequence...
View ArticleUsing the objection mechanism
Hi all,I'm trying to use the objection mechanism to coordinate between different sequences.Initially I used "TEST_DONE" but I saw that when the counter reach 0 it automatically start "end of test"...
View Articlexrun cannot initialize values
Context: a digital design, with memory elementsGoal: run power simulations with VoltusConditions: need to run the behavioral simulations using systemverilog testbenches where it is really important to...
View ArticleWhy xrun timescale does not comply with SV-2012 spec?
In SystemVerilog 1800-2012 spec Section 3.14.2.3, there is below content:" The time unit of the compilation-unit scope can only be set by a timeunit declaration, not a `timescale directive. If it is...
View ArticleRegression with Vmanager
Hi,I am new to using Vmanager and I have multiple vsif files for lunching the regression of multiple blocs.But I would like to have an automatic regression launched every week for example with a...
View ArticlevManager Failing due to BDARGF and WKUNLK error codes
I can run a regression with the count variable equal to 1 or 2 for all tests, without failure. I.e. test test_name {count : 2;}; inside of a group (.vsif script). However when I attempt to increase...
View ArticleIndago waveform is not showing after Design reload
Hi,I am facing the issue where indago waveform goes blank after I reload design. Below are the steps 1. I simulate and open the waveform in indago2. find the RTL issue, fix it and re-run3. reload the...
View ArticleDifferent result with vmanager and standalone simulation, with same seed
Hi,I am running standalone simulations with xcelium, and I have siimulation passing. When I run it in regression, simulation fails due to errors in the checkers, that I have implemented. Checkers are...
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error happen when using Debugging UVM with simvision
Recently I'm studing how to debug UVM code using simvision. I find a doc named "Debugging UVM" in cdnshelp utilty. In this doc, an example give below...
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SA Register output issue
Hello, I am implementing a 10-bit sar adc using cadence. I have been stuck in the SA Register part. I am using 22 numbers of D-Flipflops. The single flip-flop circuit is functioning absolutely fine and...
View Articlehow to get time range of each waveform file?
I use xrun to run a simulation and get a waveform directory -- "waveform.shm", which include a .dsn file and multiple .trn file. Each .trn wave file is 2GB size because I use "database -incsize 2G" to...
View ArticleHOW TO PLAY WAFFLE GAME?
Waffle Game: This is a classic game that’s been around for centuries. Players use a waffle as the basis for a playing field. They must cross the road alive to win. Anagram: This is a game where players...
View Articlehow to get time range of each waveform file?
I use xrun to run a simulation and get a waveform directory -- "waveform.shm", which include a .dsn file and multiple .trn file. Each .trn wave file is 2GB size because I use "database -incsize 2G" to...
View Article"Direction" of EEnet connection points?
I am using EEnet in SystemVerilog models to get some analog behavior of the connections (ports?, pins?) of my models.My question is about declaration of the "direction" of the ports, i.e. is there a...
View ArticleQuery on DPI_SIGNATURE_DIFF Warnings
Hi,The message from the warning is not very clear. So, can any one add more details on this warning? this will be hlepful to fix these warningsWarning! in file...
View ArticleInstance is unresolved in module
Hi,I am using Altera Quartus 19.1 Standard Edition to generate a testbench system using qsys.I am using the setup generated by it in to simulate using Xcelium. Using shell script , I am getting few...
View Articlehow to get time range of each waveform file?
I use xrun to run a simulation and get a waveform directory -- "waveform.shm", which include a .dsn file and multiple .trn file. Each .trn wave file is 2GB size because I use "database -incsize 2G" to...
View Article"Direction" of EEnet connection points?
I am using EEnet in SystemVerilog models to get some analog behavior of the connections (ports?, pins?) of my models.My question is about declaration of the "direction" of the ports, i.e. is there a...
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