In SystemVerilog 1800-2012 spec Section 3.14.2.3, there is below content:
" The time unit of the compilation-unit scope can only be set by a timeunit declaration, not a `timescale directive. If it is not specified, then the default time unit shall be used. "
But I run a simulation with xrun and find that `timescale effect timescale of compilation-unit scope. Please check below code:
----------------------------------------------------------------------------------
`timescale 1ns/10ps
class trans;
task add_delay;
$printtimescale;
$display("%t: add_delay begin",$realtime);
#2.123;
$display("%t: add_delay end",$realtime);
endtask
endclass
`timescale 1ps/1ps
module tb_top;
trans tr;
initial begin
tr = new;
$timeformat(-9,3, " ns", 15);
$printtimescale;
tr.add_delay;
end
endmodule
-------------------------------------------------------------------------------
I save this code as file tb_top.sv, and run command: xrun tb_top.sv
Then, below info print:
Time scale of (tb_top) is 1ps / 1ps
Time scale of (worklib.$unit_0x35beeaed::trans) is 1ns / 10ps
0.000 ns: add_delay begin
2.120 ns: add_delay end
xmsim: *W,RNQUIE: Simulation is complete.
In my opinion, class trans should have timescale of 1ps/1ps, which is same to tb_top.sv. The first timescale(1ns/10ps) should not take effect.
I've tried Synopsys VCS, it print below info:
TimeScale of tb_top is 1 ps / 1 ps
TimeScale of $unit is 1 ps / 1 ps
0.000 ns: add_delay begin
0.002 ns: add_delay end
This is what I expected, I think VCS works well.
Does anyone know why xrun does not comply with SV spec?
Thanks!