Recently I'm studing how to debug UVM code using simvision. I find a doc named "Debugging UVM" in cdnshelp utilty. In this doc, an example give below steps:
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For example:
> xrun -access rwc -linedebug -gui -uvm +incdir+../sv ubus_tb_top.sv -uvmtest sv:test_2m_4s
This example uses -access, -linedebug, and -gui to provide access to design objects and source line numbers, and to invoke SimVision at startup. The -uvm option enables UVM features. The +incdir+ option is used here to specify the directory in which the source files are located. When xrun looks for the top-level source file, ubus_tb_top.sv , it includes ../sv in its search path. The -uvmtest option specifies the top level of the hierarchy, test_2m_4s. The sv: prefix indicates that the top level is written in SystemVerilog.
This command starts SimVision with its default window layout. That is, SimVision opens a Design Browser and a Console window, as shown in Figure 1-1. The Design Browser displays the design hierarchy, and the Console window lets you run the simulator and SimVision through their Tcl command interfaces. SimVision provides several built-in layouts, including a UVM debugging layout. It also lets you create your own layouts.
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But,after I use this command under uvm example directory, althrough SimVision window appears:
1. it's not same to Figure 1-1. In Design Browser, under "simulator", there is no "UVM" hierarchy; (Please refer attached picture)
2. when I click "run" button, this error happen and simulation stopped:
xmsim: *W,MLUVMDEPR: The ML-UVM legacy solution is being deprecated in Xcelium 2016.11 and will not be included in Xcelium 2017.04. The Cadence support team can provide documentation describing how to migrate from the legacy ML-UVM to UVM-ML.
xmsim: *F,MLUVM05: -uvmtest or -uvmtop argument 'test_2m_4s' has been specified in language 'sv', but no adapter for that language has been registered. Use the Cadence utility 'xmhelp xmsim MLUVM05' for more information.
Does anybody know why this happen? Thanks a lot!
