"Direction" of EEnet connection points?

I am using EEnet in SystemVerilog models to get some analog behavior of the connections (ports?, pins?) of my models.

My question is about declaration of the "direction" of the ports, i.e. is there a difference in declaring an EEnet connection point as input, output or inout?  If so, what is the difference?  I am using ADE Explorer as simulator in a Virtuoso environment.