Clik here to view.
xmvlog warning: *W,DUPATR duplicate attribute name (trans)
When I use xrun to do simulation, many warnings are reported as below:-------------------------------------------------------------------------------file: /proj/example/rtl/axi2local.v (* covered_fsm,...
View ArticleClik here to view.
analog assert property doesn't show $display $error in both log file and...
I want to know how to enable the $display/$error output defined in the assert property. I don't see it output in the log file.Here is the system Verilog code:##########start of sv...
View ArticleClik here to view.
OVL assertions Library and INCISIVE152
I am new to Cadence tools and the current project is using Incisive 152/Verilog/SV. I want to add SVA using the the OVL library, and I am looking for pointers on how to compile and use the std_ovl from...
View ArticleReading simulation time to a variable
Hello,Does anyone know if it is possible to read the running time and, then store it into a variable using TCL? Imagine that a simulation is running. Every time it is simulating the time moves, when...
View ArticleClik here to view.
how to merge coverage for each instances of the agents
I am having a coverage class like this:covergroup dst_addr_cov @(drv_dst_addr_event); dst_addr_cp: coverpoint cov_dst_addr { ignore_bins invalid_dst_addr = {19, 24, [27:59], 64, [65:$]};}endgroup :...
View ArticleAMS Advanced Testbench Reuse Flow: RAK
Hi, How to drive the virtuoso schematic using a UVM test bench. ?...
View Articlehow to get time range of each waveform file?
I use xrun to run a simulation and get a waveform directory -- "waveform.shm", which include a .dsn file and multiple .trn file. Each .trn wave file is 2GB size because I use "database -incsize 2G" to...
View ArticleInstance is unresolved in module
Hi,I am using Altera Quartus 19.1 Standard Edition to generate a testbench system using qsys.I am using the setup generated by it in to simulate using Xcelium. Using shell script , I am getting few...
View ArticleHow to create a counter of edges using the Simvision Waveform Viewer
I am using Simvision for my debugs, I want to create a counter using either posedge or negedge of the signal.I dont see any option to do so in Simvision, can someone let me know how to do this ?
View ArticlePad's to Allegro Translator 17.4
Hello Forum,I am trying to translate a old Pad's project to Allegro 17.4, looks like it is creating the netlist fine, but in the pads_in.log there is a message at the end,ERROR: Subclass name...
View Articlereport unused verilog packages
Hi,Is there any tool from Cadence that can report unused Verilog packages? Often the import MyPackage::* statements are left at the top of a module declaration even though the code that was using them...
View Articlehow to save waveform signals to a file using tcl command?
Hi.In the manual of SimVision in one place I see that there a tcl command "waveform" that allows saving waveform using a command. But looks like this command does not exist, it is not in the list of...
View ArticleHow to remove glitch from Asynchronous UVM TB?
Hi All,In our UVM_TB, driver is full of fork join and we drive addr, cmd and data. We are using cadence, xcelium tool. Enabled the event while probing for simvision to see the glitch:probe -default...
View Article[Xcelium]Simulation passed but getting the xmvlog E,UNSRFA error during...
HiI ran simulation of a design using Xcelium, Questasim and Riviera. For this design, all simulations passed but however for Xcelium, during compilation of an encrypted library file, the following...
View Articleinternal exception Large VHDL Memory
Hello,I am using cadence Xcelium for simulation and as I run the elaboration step, i am seeing the following message and the simulation process stops - xmelab: *W,LARGEM: Large VHDL memory (134217728...
View ArticleClik here to view.
different results from formal verification and simulation
I wrote an a simple assertion and tried proving it with jasperGold fpv and simVision but they both gave opposite results. Can anyone help ?assertion --> clk_property: assert property ( @(posedge...
View ArticleWhy does this assertion behave like this?
Hi everyone!I'm currently watching the lessons for the "SystemVerilog Assertions" course, and while doing the lab exercises I incurred in a behaviour which I can not understand. In lab 4, which...
View ArticleClik here to view.
unable to route , showing DRC cursor
Hi,I am trying to connect a part to chassis ground and Allegro is not allowing me to make the connection for some reason. Here are some pictures to help:The first picture indicates that there should be...
View Articlecode coverage block analysis
Hi team,I am analysing code (block) coverage, I need help with the following;LINE1: always @(cmd_enable)LINE2: beginLINE3: action1: assignLINE4: action2: displayLINE5: endin imc coverage report, I was...
View ArticleRunning "small environment" on specview
Hi all,I'm new in the functional verification "world" and I'm trying to create a small environment where i can test my code easily.For that i wrote a simple code, where I generate a clock for my...
View Article