Context: a digital design, with memory elements
Goal: run power simulations with Voltus
Conditions: need to run the behavioral simulations using systemverilog testbenches where it is really important to initialize the values of all elements, aiming to avoid undefined values in the signals, in the post-simulation exported VCD waveforms. For that I used the xcelium simulator's command -xminitialize
the list of nets, registers, flipflops and memories initialized and the value exactly is done with the option below, and it worked
However the nets are not initialized, check the screenshot Post
/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/30/gtkwave.png
p.s. the full simulation is invoked by a command of this structure
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xrun -stats -ieee1364 -errtcl_verbose -access r -timescale 1ps/1ps -top tb_full -v200x -64bit -ALLOWREDEFINITION -gui VHDL/file1.vhd VHDL/file2.vhd Verilog/file1.sv Verilog/file2.v -linedebug -sv -xminitialize rand:4 -xminit_log init_list.log tb_file1.sv
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thank you on any advice on how to run this correctly