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bind procedure doesn't work if target VHDL unit is from a library
I am trying to make a bind between a system verilog module and a vhdl unit which is part of a library and i get the following error: example_i : entity work.example(sv) port map (a =>...
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ncelab: *F,DLNOLK: Failed to get a exclusive lock on library ...
I keep seeing these errors:ncelab: *N,DLWTLK: Pausing until a exclusive lock can be established on library Xncelab: *F,DLNOLK: Failed to get a exclusive lock on library XWhere X is a library residing...
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Missing symbols in UCIS shared library
Hello,I am working with INCISIVE UCIS version 15.1. Unfortunately some functions (for example "ucis_CreateHistoryNode" and "ucis_SetTestData") which are defined in UCIS header are not available in the...
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forcing signal to hierarchical connection in SystemVerilog when in...
Hi Cadence, allI know it is possible to do hierarchical assigns/forces from the testbench. e.g:assign clk = chip_top.digital_core.some_clock;I would like to do this kind of stuff from the ncsim...
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Jasper connectivity check
** Did not find forum for Jasper tool. Filing here **I am writing rules for connectivity app. Here, I am interested to write rule for a signal that is input to a module. It is expected to go through a...
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Tutorial on NCsim
Hi,I'm learning how to use ncsim and I have done so many research on Google. But what I found out was that most of the blogs are complicated to understand. For most of them, there are pre-requisites...
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How to run multiple testcases for regression using NCsim?
Hi,I would like to do a regression and it requires multiple testcases.I did this by writing a Bash script which loops until all the testcases are simulated.However, this loop will repeatedly compile....
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licqueue is not working
I put -licqueue in irun but I noticed that it is not putting it in the queue.I can still have the license checkout error below:ncsim: *F,NOLICN: Unable to checkout license for the simulation. (flag -...
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Covered in Formal
In formal parlance, I would like to know what cover/covered means.For all the assertions, an equivalent cover property is shown. An example would help ..
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How to make *E to flag as UVM_ERROR
Is there a way to make *E to flag as UVM_ERROR?Sometimes my testcase is passing (meaning no UVM_ERROR, UVM_WARNING, and UVM_FATAL) but when I check the log_file, it is flagging an NCsim error (or the...
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Simvision plugin problem
Hi,I'm trying out a small plugin for simvision.Here the plugin expects a signal path from the user using tk entry widget, and assign it to a variabe sigPath.I have tied this script as a command to a...
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vManager API
Hi all,I would like to use the VAPI and especially the regression runner to launch several sessions (vsifs) one after each other, with some timing in between the starts of teh vsifs. I am trying to get...
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HAL: turn on a rule in the design_info file
Hi,I am trying to turn on a rule, that is turned off into the def file, into the design_info file for a certain part of the modulefor instance, in the def file, I haveINSTNM {level=4} {off}and in the...
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NCSim 15.10 fails to execute VPI function
Dear all,at our institute we are using Cadence Incisive for simulating behavioral RTL designs of open-source microprocessors. So far, we used an older version (12.10) with which everything was running...
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Capacitor model SystemVerilog
Hi to everyone, I'm working on systemverilog code for my mixed signal IC, to improve the velocity of the simulation. For the resistor and capacitor connected to ground i use the model from cadence, but...
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ADDRESS Mapping issue in RAL in UVM
Hi, I've the following declaration in reg_block; class reg_block extends uvm_reg_block; .......................................... i2c_map =...
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NCSIM selective compile
Hi, I have a question regarding ncsim digital simulation. Hope this is the right place to post.I have a huge design that takes a long time to compile and elaborate before starting the sim. For...
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Post place-and-route SDF back-annotation fails when using Verilog...
Dear all,I'm working on a digital design with a top-level module that requires to declare some I/O ports with a combination of Verilog packed and unpacked array syntax in order to have a more compact...
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Iterator Index Query is having a compile error
I'm having a compile error when using the iterator index query of the array methods.The compile error says, "Hierarchical name component lookup failed". It points to index.The code is below,Is this not...
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Command that does not consider the coverage of a failing test to the coverage...
When a test fails, the coverage for it should not be considered on the coverage record.Is there a command for it? Or is this done on the script by deleting the test_*** folder associated with it?Thanks.
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