ADDRESS Mapping issue in RAL in UVM

 Hi,

    I've the following declaration in reg_block;

class reg_block extends uvm_reg_block;

 .....................

.....................

       i2c_map = create_map("i2c_map",'h0,'h1,UVM_LITTLE_ENDIAN);
   
       i2c_map.add_reg(u_ControlReg1,8'h00,"RW");     

      i2c_map.add_reg(u_ControlReg2,8'h01,"RW");

 .........

   lock_model();

endclass

During simulation,I observed the following issue;

UVM_WARNING /home/moduru/Documents/samples/uvm_ex/uvm_lib/CDNS-1.2/sv/src/reg/uvm_reg_map.svh(1633) @ 0: reporter [RegModel] In map 'm_i2c_reg_block.i2c_map' register 'm_i2c_reg_block.u_ControlReg2' maps to same address as register 'm_i2c_reg_block.u_ControlReg1': 'h1

Please let me know how to resolve this?

regards,

omahee