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Reg: generating a .vsif file before running a regression in vManager 15.10
Hello,We are trying to understand the vManager tool and here are the some doubts we are stuck with:1. How do we create a .vsif file to run a regression in the vManager tool?2. How to link the spec,...
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Error of undeclared identifier while calling c-function in VHDL with ncsim
I am getting error of undeclared identifier while calling c-function in VHDL with ncsim.I am trying to call C-functions existing in a .so filed - c_api.so inside a VHDL file, something like:begin...
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Using EEnet in SystemVerilog models
I'm not able to figure out how to use EEnet type in a SystemVerilog model. Objective is to have multiple cells driving and loading the same analog node. So simple with Verilog-AMS, but so FAST using...
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Verification of connectivity at top-level
How do you verify the connectivity at the top-level? How to make sure a user has not messed up a[m:n] with a[n:m]? Do you generally use simulation and toggle coverage to verify this or formal?
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Transition model of the hardware design by Cadence IFV
Hello,I wanted to know how the transition system of the hardware design is extracted from the Verilog code of the system by the Cadence IFV tool. As far as I know, model checking tools synthesize the...
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Simulation in NCSIM
NCSim simulation What are the steps to be taken care to perform simulation of PCIe communication in NCSIM for two different FPGA devices?FPGA 1 device (Kintex Ultrascale) - PCIe(Gen3 x4) is...
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ncelab: *E, CUVPOM: Port name '{*Name Protected*}' is invalid or has multiple...
hi,when I elaborated some protected code with ncelab, there was an error occuring, as follows,ncelab: *E, CUVPOM: Port name '{*Name Protected*}' is invalid or has multiple conections.so would like to...
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ERROR : Object found for name dut.register but language domain is not...
Dear all,I face a problem defining the hdl path of the register, trying to do the backdoor access. It says, object (register) found for name dut.register but language domain is not supported. Any ideas...
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Regression Testing in UVM
I would like to know if it is possible to run different test cases in regression mode in a single simulation in NCSIM. My test bench consists of Xilinx MIG which needs to be calibrated (takes time)...
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Migration from UVM1.1 to UVM1.2: Problems with Register Viewer + Warnings
Dear All,I have recently migrated from using UVM 1.1 to UVM 1.2. I have noticed there are additional warnings and problems with UVM Register Viewer in Incisive 14.10.011 version.UVM_WARNING : reporter...
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Running Multiple Test Cases back to back (Regression)
Hi,I am currently doing a verification project in NCSIM which has Xilinx MIG as one of its component. MIG needs to be calibrated (takes time) before simulation. Right know this initialization needs to...
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Query regarding the usage of analog assertions in systemverilog file
Hi Team,Presently I am developing a test-bench that include assertion checks for some analog signals. But facing some issues as described below.1. I used the $cds_get_analog_value(hierarchy,"type") to...
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ncelab and ncvlog version error conflict
I am trying to follow a tutorial on how to use NClaunch interface to compile and elaborate verilog files. There seems to be a version conflict when I get to the elaborate step. Here is the error I...
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IRUN command to change the Assertion severity level
Hi, I'm new to assertions and i've written the following property in my interface. property p1; @(posedge clk) (data == 2'h2) ##[1:6] (data1 == 2'h2); endpropertyalways@(posedge clk) assert...
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cover property evaluation error
Hi, I've written the following cover property;property p1; @(posedge clk) (data == 2'h2) ##[1:6] (data1 == 2'h2); endpropertyalways@(posedge clk) cover property (p1);When it hits first time true...
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Any alternative way to connect an internal DUT's signals to TB's interface's...
Hello,I have a DUT with a controller and memory inside it - connected via an interface-protocol, say AXI.Then I have a TB with DUT_inst & Interface_inst. The purpose of this interface_inst is to...
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compilation error
Hi ,I am getting following error whenever I try to compile a file using ncverilog or irun command :irun: *W,WKWTLK: Waiting for a Exclusive lock on file...
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UVM_CMDLINE_PROCESSOR working issue
Hi, I'm trying to get value from command line using UVM_CMDLINE_PROCESSOR but couldn't extract the value from command line with the following trail code;class onscl extends uvm_object; extern...
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Several entity/architecture pairs for the the same cell?
Hi all,Is it possible to place a pure VHDL and VHDL-AMS models of the same component inside the same cell?.I would like to store all my models inside the project library, side by side with their...
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shm_probe
Hello ~I am ASIC engineer.How can i dump shm just depth 1 step by $shm_probe is it possible?I mean just dump top's nets and top's instance level except instance's instance thanks
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