forcing signal to hierarchical connection in SystemVerilog when in interactive mode

Hi Cadence, all

I know it is possible to do hierarchical assigns/forces from the testbench. e.g:

assign clk   = chip_top.digital_core.some_clock;

I would like to do this kind of stuff from the ncsim interactive console. Can you please advice whether this is supported by ncsim and, if it is not, why ?

Thanks