Clik here to view.
unable to simulate VHDL record constant assignment through component port
Hey,I am not sure if this is the right board, kindly move it to the right one.When trying to simulate the attached test-case using Xcelium, I am facing below error as can be seen in the snapshot...
View ArticleERROR: VRsrc instance behavioral_modelling_doubler_full.I26.S0o node P...
<EE> ERROR: VRsrc instance behavioral_modelling_doubler_full.I26.S0o node P unconverged at T=101005ns<EE> ERROR: VRsrc instance behavioral_modelling_doubler_full.I26.S0o node P unconverged...
View ArticleClik here to view.
Error : lps_1801 elaboration : *E,MTOMDU : More than one unit matches...
Hello,I am listening Low power simulation with IEEE 1801 UPF v22.09 Module 04 : simulating a UPF based low power RTL designExample of module4 in nano CPU of DebuggingLPS/examples attempted to...
View ArticleClik here to view.
xcellium compiles every RTL hierarchy into a "library_cell", how do I get rid...
Hi Cadence, I use a vendor provided makefile (really huge) with ncsim simulation. In the GUI I can see an extra "Library Cells" hierarchy is added to every RTL file. While I compile the same RTL in my...
View ArticleWindows/ Mac compatibility for Cadence softwares
Hey,I'm an incoming master student and I not sure what kind of laptop OS would be best to learn and do projects in Design Verification (with cadence or synopsys softwares).Should I go with MacOS or...
View ArticleXcelium 21.09 Installation setting and manual(?)
Hi, all. I am new to Xcelum functional verification. I installed Xcelium 21.09 and spent 1 hour searching for the binaries like xrun.It is so weird that the major binaries are listed in tools/bin.I...
View ArticleXprop reset setting in tcl
I am using the flip flop output as reset.So, I gave the following reset declaration to tcl.reset ~ff_name.outputHowever, xprop shows the error (ERS026) Invalid reset expression the following reset...
View ArticleMISE(Multi-Snapshot Incremental Elaboration)with Gate level files
Hi, I am working on MSIE both with RTL files and gate-level files.Creating a primary snapshot and elaborating with my testbench in a simulation with RTL filelist works well,but there are some errors...
View Articlewhy my xrun does not compile UVM library package automatically？
I have a very small module level UVM environment. I add "-uvmhome CDNS-1.1d" option with xrun, but it report some compile error. It seems that xrun does not compile UVM library automatically. I use...
View ArticlevManager Error "Failed to send chunk"
After creating a vaild VSIF file, and launching from the vmanager gui. this message occurs "Failed to send chuck"with a path to the chain_0/static_chain_exp. What is the cause of this error and how to...
View ArticleXcelium simulator is not running when vhpi application is loaded.
I am able to load and execute a vhpi application that can read the vhdl hierarchy, and can put and get values.The problem I am having is that when I put a value on to. say an input, it does not...
View ArticleWhat is Xcelium's equivalent of VCS's deraceclockdata option?
VCS has deraceclockdata compile time flag which ensures that irrespective of the coding style clock and data updates do not occur in the same evaluation step.Does Xcelium have something similar?
View ArticleMemory Viewer formatting
I have a memory in my design that has parity bits inserted after each byte in a 32-bit word (each word is 36-bits w/ parity). How do I display this memory in the simvision memory viewer such that the...
View ArticleSystem Verilog: always @( * ) is not working, but explicit declaration always...
In my code I am using the following sensitivity list declaration.Problem: This code never enters the always @( * ) block - thus the supply check always fails (supplyOk=0)://checking supply`ifdef...
View ArticleFree version of NC-Verilog
I got a model in Verilog which according to the creator is only compatible with the NC-Verilog compiler. There is any free version of it or an another way to run it as Qsys component. Or is there a...
View ArticleHow to Map covergroup from present regression database to a reference vPlan
HiI'm trying to Map Coverpoints to a new vPlan, But according my other requirement in project I had to do load reference vPlan. Now after doing reference vPlan I could able to get all the sections...
View ArticleClik here to view.
Irun error MXINDR with a verilog PLL model wrapper written in VHDL, any way...
Hi Cadence, I have a VHDL wrapper of a PLL behavior model. The VHDL routes XO output CLK_P & N to the PLL as differential input. In the PLL model the same signal goes through 7 hierarchies to a...
View ArticleXcelium waveform dump into custom directory
Does anyone know if there is an option in Xcelium to change the location of the waveform dump? Currently in my tcl script I usedatabase -open -shm -into waves.shm waves -defaultand this way I have the...
View ArticleIs it possible to connect two workspace/simulations via DPI-C?
I have two projects, both are very large and are the two sides of a serial transceiver, each has billions of gates.The two projects simulate in the respective databases so merging database is not...
View Article