How to assign values to an item without randomization (without constraint)?
Hi all!I wrote some code for uvm_item and uvm_sequence. It generates 5 random items using "constraint", but then I need to create the last item with defined values of item_incode variables (for example...
View ArticleDPI Calls
Hi, I have a question regarding DPI calls. I read that always_ff is modelled as a thread. so If I have two always_ff calling the same DPI function on same clk, will it behave like multithread on C/CPP...
View ArticleHi i need help regarding one scenario i have two functions defined one basic...
Hi i need help regarding one scenario i have two functions defined one basic tc and other sqc .... for now mu_value vaues based on the condition is getting calculated based on the given condition and...
View Articlecan't import uvm_ml for using sv test with e component
In my test I have : import uvm_ml::*;after compilation with : xrun -V93 +UVM_TESTNAME=test_cosim -ml_uvm ...I got an error:xmvlog: *E,NOPBIND (...) package uvm_ml could not be boundI run with xrun(64)...
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How to solve the error:"Function xmdbg_fatal not define"
hiI run xmsim in a mixed environment( including verilog & c++ (using dpi to in import)), and the simulation is end with a error: SIGUSRI read cadence document and try to use gdb to find the problem...
View ArticleHAL linting with parameters/generic
Hi, I am on the design of a generic IP and as usual I wanted to check my code with HAL but unlike usual, I have a parametrized design, I mean I have a lot of RTL that are include in "if generate"...
View Articlexrun - prioritizing licenses by users
Hi,I have a system that keeps running tests using the xrun command. The system is active during night and I'm interested it will work during the day too.For that, I need to give prioritization of...
View ArticleHow do I pass a type of class as a parameter to sequence?
I have a test0 class, where I should pass the parent "item_program" class and its child "item_program_testX", but the child should always be different (one test class - one child):class test0 extends...
View ArticleHow can I exclude simulation failed test cases when coverage is merged...
Hello, I build up the environment for automatically extracting coverage.I want to exclude failed test cases when simulation. For this, I think that coverage database has test result pass or fail and...
View ArticleNeed some help for $sscanf
Can anyone tell me how i can supress few strings or integers while reading with $sscanf.I read a line from a file into a string. there are few strings and integers seperated by white spaces in the...
View Articlehow to generate waveforms with 1) xrun 2) xmsim 3) irun commands ?
Can anyone please help me with commands to create waveform with all 3 ?
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SimVision Expression Calculator Issue/Help
Hi, I am trying to use the expression calculator to count transactions on an AXI Lite bus. I used the expression calculator to create a signal by ANDing TVALID, TREADY and CLOCK. The problem is (as you...
View ArticleMerge command error
When I tried to merge all my coverage ".ucd" files generated in IMC , its showing this sort of warning :*W,MGURTS: The merge command could not resolve the run specification cov_work/scope/test_01....
View ArticleEnabling code coverage deeper into SV function calls
Hi all, I have a package of functions, many functions have a test case associated with them that exercises that function over most of its input variables.The design also contains two RTL modules...
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SystemVerilog task() output signal does not have correct value
I started recently with SystemVerilog (lets say Verilog in general) and I am trying to create a "task()".I am using the Virtuoso/Xcelium AMS environment and want to generate a pulse with configurable...
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Internal SV signal not created properly when simulated with xrun/simvision
When simulation the SV files with Virtuoso-AMS (Xcelium), I get the internal signal "analogIn" simulated properly:But simulating the same code with xrun/simvision, teh same signal is "0" all the time...
View ArticleCreate image from vcd file
Hello!Is there a way to convert VCD file to an image using a script for automated mixed signal simulation results?Using Simvision I can print window and get the job done, but I would want to automate...
View ArticleJaspergold -- Net does not have a driver
Hi In Jasper gold >>>Even after assuming a value for the declared signal --- Seeing warning as net "signal name" does not have a driverex_signal[4] ---> ex_signal[0] ,ex_signal[1],...
View ArticleXcelium: Link a third-party library to your simulation
Dear all, I have a VHDL digital design that I want to synthesise and simulate using TSMC180n Tech. I have successfully generated the netlists based on the TSMC tech using Cadence Genus (reads .vhd and...
View ArticleCan queues be used to drive RTL?
This may well be a case of my not being able to see the wood for the trees or generally doing something stupid, but I thought I'd ask anyway.I'm trying to interface a bus driver with some DPI code and...
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