unable to simulate VHDL record constant assignment through component port

Hey,

I am not sure if this is the right board, kindly move it to the right one.

When trying to simulate the attached test-case using Xcelium, I am facing below error as can be seen in the snapshot below:

The same code simulates in Questa but the constant should have a value of 8 instead it has 0x8000_0000, (-2147483648). The code seems valid to me, kindly share your thoughts what could be done to simulate it?

Thanks,

Hu