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unable to simulate VHDL record constant assignment through component port
Showing live article 981 of 1093 in channel 3711457
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Language: English
Channel Number: 3711457
Article Number: 981
Date: February 28, 2023, 6:02 am
URL: https://community.cadence.com/thread/56826?ContentTypeID=0
GUID: 75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:81efe4d5-3ed6-4122-9504-8e38f82c7cad
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