Irun error MXINDR with a verilog PLL model wrapper written in VHDL, any way to workaround?

Hi Cadence, 

I have a VHDL wrapper of a PLL behavior model. The VHDL routes XO output CLK_P & N to the PLL as differential input. 

In the PLL model the same signal goes through 7 hierarchies to a leaf cell where the final line is "tranif1 #(1*5) tgate (OUT,IN,en_diff);". 

The PLL model is written such that in layer 2K+1 of hierarchy the CLK_P & N are defined as INOUT, while on layer 2K it is defined as input. VCS seemed to work fine and generate a schematic below. 

xcelium_21.09.s007 gave the following error, 

xmelab: *E,MXINDR: VHDL port of mode IN, :a:b:c:PLL_shell_inst<local>FREFCMLN (/dir/rtl/pll_wrap-rtl-a.vhd: line 27), is connected below to a Verilog port, :a:b:c:d_inst.FREFCMLN (/dir/beh/PLL_shell.v: line 31), with drivers.

Are there any switches in xcelium to make it work? 

Thank you in advance.