System Verilog: always @( * ) is not working, but explicit declaration always @( s1, s1, s3) is working

In my code I am using the following sensitivity list declaration.

Problem: This code never enters the always @( * )  block - thus the supply check always fails (supplyOk=0):

//checking supply
`ifdef SUPPLYCHKOFF
   logic supplyOk = 1;
`else
  logic supplyOk = 0;
  always @( * ) begin
    $display("TIO MUX GATE always block was triggered");
    //range check
    if( VSS inside {[minGND : maxGND]}) supplyOk = 1;
    else supplyOk = 0;
end
`endif

BUT when the sensitivity list includes the explicit inputs, then it is working as expected and sets "supplyOk=1":

//checking supply
`ifdef SUPPLYCHKOFF
   logic supplyOk = 1;
`else
  logic supplyOk = 0;
  always @( ATB_TG_EN, ATB_TG_EN_B, VSS, TG_in ) begin
     $display("TIO MUX GATE always block was triggered");
    //range check
    if( VSS inside {[minGND : maxGND]}) supplyOk = 1;
    else supplyOk = 0;
end
`endif 

Does anyone have an explanation for this behavior ?

I am using  ICADVM20.10.310 with XCELIUM22.09.002.

This supply-check code snippet is used in many other models and working there perfectly fine. Only in this model, it does not - and I do not find the reason.

I would like to attach the complete model file, but did not find a way to do it in this forum.