Dear all,
I have a VHDL digital design that I want to synthesise and simulate using TSMC180n Tech.
I have successfully generated the netlists based on the TSMC tech using Cadence Genus (reads .vhd and generates .v netlists).
When I want to simulate the generated netlists, I have the following error message reported tens of times:
"xmelab: *E,CUVMUR (./Clk_Divider_m.v,12|26): instance ':Clk_Divider_tb(bench):uut@Clk_Divider<module>.RC_CG_HIER_INST0@RC_CG_MOD<module>.RC_CGIC_INST' of design unit 'CKLNQD1BWP7T' is unresolved in 'worklib.RC_CG_MOD:v'. INVD0BWP7T g300(.I (reset), .ZN (n_32));"
I'm assuming that the simulator cannot find the definitions of the cells (mentioned in the netlist) in its library.
My question is: How do I correctly link the .lib file of the TSMC tech so that Xcelium can resolve those cells?
Many thanks
Anas