HAL linting with parameters/generic

Hi,

I am on the design of a generic IP and as usual I wanted to check my code with HAL but unlike usual, I have a parametrized design, I mean I have a lot of RTL that are include in "if generate" (Verilog) and depending on module parameters values. The issue is that HAL is analysing (as far as I know) only the set of parameter value that I gave to him and not all the possibilities, so I must launch HAL multiple times with all possible values for it to analyse all my RTL.
Is there a way to do that in a better way ?
To be noted that I also have a non-regression test with all the possible values, so if HAL could aggregates multiple simulations (as for IMC that does it for code coverage), it would be great too.

Jeremie