Clik here to view.
Timing and scheduling actions in vManager
Hi all..I wanted to know if it is possible to generate the regression reports(in the csv file format) by vManager tool of Cadence at regular intervals of time(say 30 min or 1hour) automatically? Also...
View ArticleClik here to view.
Efficient way to create vpi handles and callbacks
Hello Everyone,Currently I am using following VPI calls to create handles and callbacks to my design hierarchal signals.vpiHandle handle = vpi_handle_by_name( , );cb_handle =...
View ArticleClik here to view.
JasperGold Connectivity check
Hi Cadence,I got below issue at "analyze RTL" step in Jaspergold Connectivity Check App.Is there any command option to solve it ? [ERROR (VERI-1817)] ...: parameter initial value cannot be omitted in...
View ArticleClik here to view.
Disable VHDL assert using xrun
Hi,I am trying to disable VHDL assert but I was not able to find the option used by xrun to do that.Anyone can help ?Thanks.NabilPS: following an example of the code implemented and its...
View ArticleClik here to view.
Export sessions to csv in cadence vmanager tool
Hi all..I need to generate the regression report (of selected sessions) in the form of csv file in cadence vManager tool in Batch mode using batch mode commands. The command I used is -vmanager...
View ArticleClik here to view.
Viewing Classes in Simvision
Hello all,I've just started creating a more robust test bench structure using classes. I've never tried to use classes in verification before and so I'm having some trouble understanding how to view...
View ArticleClik here to view.
PVS rule file syntax check
Hello Cadence team,I have been using cadence PVS for some time and I have noticed that PVS has the ability to show syntactical errors in the rules files. Basically, we get a red box around the rule...
View ArticleClik here to view.
Reading an input file using std.textio
Hi,I 'm having a problem trying to read an input file on a testbench on Incisive.I believe the problem is due to a wrong file path, but I tried to copy the file to several folder and none worked.The...
View ArticleClik here to view.
adder functional verification
Hi all,I have the extracted view of a 32-bit adder in subthreshold. Is there any tool in cadence to check the yield of the circuit? ThANKS,
View ArticleClik here to view.
How do we use the concept of Save and Restore during real developing(debugging)?
Hi All,I'm trying to understand checkpoint concept. When I found save and restart concept in cdnshelp, There is just describing about "$save" and "xrun -r "~~~".and I found also the below link about...
View ArticleClik here to view.
vManager tool gives this error-"Error:Project Environment Selection is...
Hi all..I need to generate the regression report (of selected sessions) in the form of csv file in cadence vManager tool using batch mode commands. The command I used is -"vmanager -exec cmnd", where...
View ArticleClik here to view.
Verifying Configuable RTL with JasperGold
Currently I am trying to verify an RTL file which is created with Parameters and Generate statments. This module is made this way so that I can be used multiple projects and adapt to the parameters...
View ArticleClik here to view.
Issue with merging code coverage with different parameter values written in...
Hi, I've ran couple of tests for below RTL code. One with parameter COUNTER equal to 1 and another test with COUNTER equal to 0. Now, I could not merge the coverage for both tests cases. Command used...
View ArticleClik here to view.
How to Setup Xcellium to run on Ubuntu
Yes, I know its not a supported platform, it should be.Most of the companies I work with run Ubuntu. Does anyone have a list of steps/libraries that need to be installed to get Xcellium working on...
View ArticleClik here to view.
System Verilog Assertions
Hi all,I have the following scenario for writing assertion.Signal 'A' rises two cycles after 'B' falling. The high period of 'A' is, 70 + (var_value) clock cycles.I wrote two assertions to check this...
View ArticleClik here to view.
a test runs differently if I use the -svseed command line switch or I set the...
Hi dear all,I am at a customer working on a SystemVerilog UVM - based verification environment…without going (yet) too much deep in details I have that starting a simulation with a command line such...
View ArticleClik here to view.
Is it possible to do formal verification of firmware related functions in...
I am currently trying to do formal verification of safety mechanisms in JasperGold. However, part of the safety mechanism is first implemented in Firmware and later, based on this, safety flags are...
View ArticleClik here to view.
UVM Register viewer
Hello all,I have implemented UVM Register model. I am able to check the values at the Interface level, but i cannot see the register values in the UVM Register viewer.Can anyone help me in fixing this...
View ArticleClik here to view.
Macro in `include compiler directive.
Hi there, SystemVerilog community,I would like to run several instances of a simulation, each with a separate include file rom a different path. I would like to hand a +define+FILEPATH to the...
View ArticleClik here to view.
Initiating tcl script in Xcelium
Hi everyone,I'm new to scripting and so far it has been really overwhelming. I want to run a tcl file using a command directive in Xcelium, and so far i've had no luck. The tcl file was initially made...
View Article