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How to effectively browse verilog source in Cadence
Hi,I know simvision can do source/load driver tracing but I believe it is more aimed at actual value tracing more than "browsing" through the code. I.e. I am looking for a Verdi style tracing, where it...
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How to effectively browse verilog source in Cadence
Hi,I know simvision can trace do source/load driver tracing but I believe it is more aimed at actual value tracing more than "browsing" through the code. I.e. I am looking for a Verdi style tracing,...
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How to make defparam disappear in netlist generated by NC-verilog in Cadence
Hi all,I am looking the option so that the defparam is not shown in the netlist generated by NC-verilog in Cadence.This is one example of the netlist with defparam:ainv_lvt I1 (net01, net02, vdda,...
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Dumping only last 1ms log file information in irun/xrun
Hi,To manage log file size. I would like to dump out the log information for only last 1ms. Is there a way to do that in irun/xrun tcl input script?There are are lot of test cases and the time duration...
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$xm_deposit in gate level simulation
Hello,i tried to deposit a value inside a register using this code:$xm_deposit("tb_chip_top_s222.dut_u.i_digtoppad.i_dig_top_pads.i_dig_top.i_volt_cfg_regs.i_cfg_3_secded.\\secded_data_r_reg[0] .Q",...
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VPlan Report- links for each test
Hi all,I would like to generate a vplan report in order to have an html link for each entity of the plan.so people that want to check if the requirment has been covered can click on the link and see...
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Voltus-Fi vpserro layers displayed
Hello everyone,I am currently adapting Voltus-Fi to the design flow (UMC180 technology).The EM/IR analysis through ADE-L seems to work (judging by changing the output plots).But displaying Results >...
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using eManager to read regression files but failed.
when i tried using eManager to read regression files but failed, so no data is available when click vplan button for verification plan map and code coverage analysis using IMC.eManager's log is...
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NCLaunch VHDL compiler *F,DLUNNE error
I'm trying to compile a VHDL code via NCLaunch. However, I keep getting the following error on the console*F,DLUNNE: Can't find STANDARD at /vlsi/apps/cadence/ius/8.2HF015/tools/inca/files/STD.There...
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Export a Breakpoint
Hi all,I was running a simulation with Xcelium in Simvision and I save few breakpoints.I would like now to run another simulation (so from a different console) and loading one of the breakpoints of...
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NC-Verilog user manual
Hello everyone,,I am not able to trace the user manual of NC-Verilog. I need it, because I am trying to solve this issue:...
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Load several shared object
Hello everyone,I have a question about DPI-C , i know i can load a shared object using irun, even if you need to call it libdpi.so to load it . But I want to load several shared object and not only...
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[IMC] Toggle coverage report
Hi,Is it possible to consider only 0->1 or 1->0 transition condition in toggle coverage report ?I mean that I want to consider that a net is full covered if one of this transition is respected...
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Efficient way to create vpi handles and callbacks
Hello Everyone,Currently I am using following VPI calls to create handles and callbacks to my design hierarchal signals.vpiHandle handle = vpi_handle_by_name( , );cb_handle =...
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VManager wrongly imports failed test as passed
Hello,I'm exploring VManager tool capabilities.I launched a simulation with xrun, which terminates with a fatal error (`uvm_fatal actually).Then I imported the flow session, through VManager ->...
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-std=c++14 support for XCC compiler in Xtensa Xplorer
Hello, I am trying to do some program with Vision P5 DSP. where I have to use some typecasting of class members and also to use templates that all are supported with the flag -std=c++14. But the...
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Design library not defined while reading module with ncsim
Hi supporters,I got the following error while I run simulation with gate netlist using Cadence Incisive (v15.20):----ncsim(64): 15.20-s076: (c) Copyright 1995-2019 Cadence Design Systems, Inc.ncsim:...
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Force cell equivalence between same-footprint and same-functionality...
For a netlist vs. netlist LEC flow we have to solve the following problem:- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call those MACRO_A- MACRO_A is...
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Export sessions to csv in cadence vmanager tool
Hi all..I need to generate the regression report (of selected sessions) in the form of csv file in cadence vManager tool in Batch mode using batch mode commands. The command I used is -vmanager...
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Simvision Schematic Information
Hi all,I would like to understand if it is possible from Simvision to get the information regarding the view of a block. In principle using the Schematic Tracer Simvision is able to find the...
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