System Verilog Assertions

Hi all,

I have the following scenario for writing assertion.

Signal  'A' rises two cycles after 'B' falling. The high period of 'A' is, 70 + (var_value) clock cycles.

I wrote two assertions to check this scenario;

1. property A_RISE;
    @(posedge clk) 
    $fell(B) |-> ##2 $rose(A);                                                //to check the dependency of A w.r.t B
    endproperty

    ASSERT_A_RISE : assert property(A_RISE);

2. property A_HIGH_PERIOD;
    @(posedge clk)
     $rose(A) |-> A[*70] ##1 A[*var_value] ##1 !A;           //to check the high period of A
    endproperty

    ASSERT_A_HIGH_PERIOD : assert property(A_HIGH_PERIOD);

Is there any better way to check both dependency and high period together?

How can we use variable cycle delays or sequence repetitions in assertion properties??

I have started to practice system verilog assertions recently only; Please provide me some guidelines to proceed with this.

Thanks