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adder functional verification
Hi all,I have the extracted view of a 32-bit adder in subthreshold. Is there any tool in cadence to check the yield of the circuit? ThANKS,
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IMC tool is not mergeing properly already merged coverage files
HI,I have 9000 test cases so I am running tests in batch of 1000 with coverage enabled and merging them using imc batch command. Till this point it is working in fatastic way. But when I am trying to...
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Support VHDL2008 in ncsim
Hello,Which option enables support of VHDL2008 in ncsim ?Thanks.
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How to export searched signal list using simvision design search to a text file?
Hi,I am using Simulation Analysis Environment SimVision(64) 15.20-s025. I have a list of signals searched and displayed using the design search window and I cant seem to find a way to export them to a...
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Merging data base with two RTL changes
Hi team,Do we have any provision to merge two different version of coverage .icc files?Example. I have generated coverage data base D1 with RTL changeset CL1. There are some changes done in RTL so...
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Is ncsim (version 12.10-s19) fully compatible with VHDL2008
Hello,When compiling VHDL source with option -V200X, I get error on this line:pixel_new := (others=>'0') when lfsr_val(15) else (others=>'1');Any comments.Thanks.
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Force X in gate level simulation
How to initialize flops not having reset pin in gate level simulation?I expected -ncinitialize to do. but it doesn't.What is the best (simple) and general way for cadence simulator ?Thanks in advance.
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UVM RAL
I am using Cadence register model. I am trying to randomize a register within model with constraint.assert( reg_model_hanldle.reg_name.randomize() with { fieldname.value == 'habcd});I get an error...
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Show all drivers for a particular signal at a particular time in ncim
Hello,The problem is expressed in subject: does exist some technique that allow to show all signal drivers at a particular timeThanks in advance.
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Verifier Access to SV Variable in Testbench
I have a systemverilog testbench that simulates fine in Explorer. It contains a logic variable that indicates pass/fail of the test. In Verifier, I can import the Maestro view as an implementation,...
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Cadence iLS course manual refers to non-existent 'training' for learning how...
I am taking the course JasperGold Formal Fundamentals. The lab manual assigns tasks that say to use a feature of JasperGold shown in 'training'. I watched all the videos and they only introduce the...
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Collect only Covergroups
Hi,i would like to collect functional coverage, but only the covergroup part. meaning i don't want to collect also data for assertions (ABV)currently i am using the flag of " -coverage u " which...
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Xcelium DPI
I am calling c functions from sv module. c functions are compiled in shared lib. I am able to call c function from sv module with shared lib.I am using xcelium xrun for simulation. I want to use...
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Is there a way to adapt vRfine file after RTL source file updated and line...
Hi,In case of we have a vRefine file(eg: expression exclusion), and then RTL source file is modified which result in line number changing,when we apply vRfine file in IMC, the exlusion can not be...
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Array of covergroup not supported
I have defined a covergroup inside a package and creating instances of it in a class as shown below:covergroup example_cg(bit en); option.name = "ex_cg"; option.per_instance = 1; ex_cp: coverpoint...
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using eManager to read regression files but failed.
when i tried using eManager to read regression files but failed, so no data is available when click vplan button for verification plan map and code coverage analysis using IMC.eManager's log is...
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using eManager to read regression files but failed.
when i tried using eManager to read regression files but failed, so no data is available when click vplan button for verification plan map and code coverage analysis using IMC.eManager's log is...
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Power Quality Requirements
Folks,I am new here but looking for expert guidance on power quality requirements for the Palladium Z1 XL?Have been asked to consider plugging these in directly to grid power without conditioning. What...
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xmelab: *E,CUVDNF (./netlist.vams,1748|8): Could not determine discipline for...
Hey experts,We are facing an error while running xrun for simulation of netlist:<SomeModule> <SomeModuleInstance> ( .() ..........xmelab: *E,CUVDNF (./netlist.vams,1748|8): Could not...
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How to netlist a VHDL-AMS generic of type "time" correctly in ADE?
Hi,while trying to transfer a working mixed-signal system model from Mentor Graphics SystemVision to Cadence Virtuoso/AMSDesigner I came across the following problem.Some of the VHDL-AMS components in...
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