Macro in `include compiler directive.

Hi there, SystemVerilog community,

I would like to run several instances of a simulation, each with a separate include file rom a different path. I would like to hand a +define+FILEPATH to the simulation and use the in the line, where I include the files. Now, what I have found out is, that an "include" directive cannot resolve macros. Is that correct? Is there a way around it? Do you have any suggestions?

Example with code:

call simulation with +define+FILEPATH "/.../..."

then use:

`include FILEPATH

-> can't be done.

Thank you for any help on this.

Michael