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Accessing Packed Arrays using Tcl Interface
I am exploring options to access and modify the contents of a packed array in the simulation hierarchy, with the aim of replicating some VPI functionality using the Tcl scripting interface.I have a...
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Spectre suddenly stops running during Parametric Analysis (ADE L)
Hopefully somebody can answer this question but, we are having trouble trying to get a Parametric Analysis to COMPLETE when running ADE simulation. Every time we run it, spectre seems to stop running...
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Promote SVA failure to uvm_error
How could the System Verilog Assertion failures be promoted to UVM_ERROR to be reported by the UVM environment?I am aware that it can be coded as:assertion_name:assertproperty(//...
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Capturing glitches in Xcelium
Hello,So I am seeing this weird behavior in my simulation where a register captures a value but nothing in the input logic cone has changed.For e.g., a <= (b & c) | (!d) | (~e &f)where a is...
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same value for a RANDC variable of base class in extended class objects
i have a randc variable "index" in c_base. i've two new classes (class_1 & class_2) extended from base_class. when randomizing the extended class objects, i observed the variable "index" is having...
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NCELAB WOUPSR errors
I have a UVM testbench which gives the following errors when I compile:$cast(arg, tr); // Need run-time casting because at compile time T1 can be scalar. |ncelab: *E,WOUPSR...
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VPI : vpiLoad iterator on vpiIntVar
According to the IEEE Std 1800-2012, VPI code should be able to determine the variable loads of a vpiIntVar or vpiIntegerVar using the vpiLoad relationship iterator. The relevant section is 37.17 of...
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How can I implement a sequential coverage?
I have an event nameddtx_intrpt_e. I want to create the following coverage: On tx_intrpt_e wait few cycles cross uarttx_dma_sreq==1.Where uarttx_dma_sreq is a port of the interface.p.s"few cycles"...
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How to disable deferred assertion error message dynamically?
Hi,I've a deferred assertion enabled by default. For example,sequence a_seq; (A) ##1 (A)[*100];endsequenceproperty a_ast;@(posedge clk)1 -> a_seq;endpropertyAt times I need to terminate the...
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Indago tcl commands
Hi,Anyone knows where I can find tcl commands supported by Indago debug analyzer app
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Coverage not getting hit when trying with IUS simulator
HiI am seeing discrepancy in cover bins getting hit , I have total 10 cover bins out of which valid 8 get hit with VCS , however with IUS none of my valid bin gets hit.I have put display prints to see...
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PSpice A/D Stuck in lite version even if I have a license dongle. How to...
I have check lmtools and the license server is functional with the dongle. OrCAD Capture says that it is full versionRunning simulation from there brings up PSpice A/D lite version instead of a...
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How to read label inside a particular instance and check its connectivity...
Hi,I have multiple instance in top cellEach instance has some labels inside it.How I can get the instance name and read the labels inside it, and check to which label(of another instance) it is...
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LVS filter pins in layout
We have some dummy devices in our analog layout. The current LVS processing ignores them, regardless of if they are existing in both layout and schematic.However, the LVS is not clean because of...
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IMC Coverage figures in ascii report differs from GUI & html report
Hi all,I have problems to get the same coverage figures shown in the GUI & html report versus the plain ascii report for a toplevel module.I am using the following script:merge -overwrite -message...
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Verilog-a implementation of TFET
I'm trying to implement TFET model in Cadence Virtuoso using Verilog-a. I'm able to create a symbol for it, but when I try to simulate it by using it in a test circuit, I get an error stating "Cannot...
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Multi Dimensional Dynamic Array Constraint support Issue in System Verilog/UVM
I've the below example for multi dimensional dynamic array randomization; Class base extends uvm_sequence_item; ...... rand integer array_of_frames[][][]; rand int...
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"weird" verilog-A problem
Hi,I am trying to generate a triangular waveform (Vstart :Vstep : Vtop) using verilog-A. Once it reaches Vstop, it should ramp down (Vstop : Vstep :Vstart), and then start from Vstart again.below is my...
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code_coverage_Error_The_design_unit...
Hi All,I am doing code coverage, receiving following error;ncelab: 14.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.TOOL: ncelab 14.10-s014: Started on Jan 09, 2018 at 12:09:19 ISTncelab...
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run_phase doesn't update SV interface signals
Hi,I am trying to set up a minimal UVM env to learn this methodology.My problem is that UVM driver doesn't seem to update the interface signals connected to DUT. Testbench can update it (clock and...
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