Hi,
I am trying to generate a triangular waveform (Vstart :Vstep : Vtop) using verilog-A. Once it reaches Vstop, it should ramp down (Vstop : Vstep :Vstart), and then start from Vstart again.
below is my code:
module ramp(clk_in, reset, Vout);
input clk_in, reset;
output Vout;
electrical clk_in, reset, Vout;
parameter real vtrans = 0.5;
parameter real tdel = 100p from [0:inf);
parameter real trise = 1p from (0:inf);
parameter real tfall = 1p from (0:inf);
parameter real V_start = 0.2;
parameter real V_step = 0.2;
parameter real V_stop = 2;
integer logic_reset, sign;
real out_val;
analog begin
@ ( initial_step ) begin
out_val = V_start;
sign = 1;
end
logic_reset = V(reset) > vtrans;
@ (cross(V(clk_in) - vtrans, 1)) begin
if (logic_reset == 1) out_val = V_start;
if (logic_reset == 0) begin
out_val = out_val + sign*V_step;
$display("out_val is %r. xxxxxxxxxxxxxxxxxxxxxxxxxxxx\n", out_val);
$display("V_stop is %r. xxxxxxxxxxxxxxxxxxxxxxxxxxxx\n", V_stop);
if (out_val >= V_stop) sign = -1;
if (out_val < V_stop) $display("out_val < Vstop \n");
if (out_val <= V_start) sign = 1;
$display("sign = %r. xxxxxxxxxxxxxxxxxxxxxxxxxxxx\n", sign);
end
end
V(Vout) <+ transition( out_val, tdel, trise, tfall);
end
endmodule
The problem is when I set Vstart=0.2, Vstep=0.2, Vstop=2, the ramp goes to 2.2, and then comes down. According to the code, it should reach 2, and then ramps down.
Further debug shows that when Vout reaches 2, the comparison out_val >= V_stop is false, where it should be true, as the simulation output log shown below. As a result, the ramp further goes up to 2.2, and then starts to come down.
out_val is 2. xxxxxxxxxxxxxxxxxxxxxxxxxxxx
V_stop is 2. xxxxxxxxxxxxxxxxxxxxxxxxxxxx
out_val < Vstop
sign = 1. xxxxxxxxxxxxxxxxxxxxxxxxxxxx
If I test it with Vstart=2, Vstep=2, Vstop=20, then the ramp stops at 20 correctly and then comes down.
I noticed this sometimes also happens at the low end, where it should stop at Vstart, but continues to go one step lower.
Very confusing to me. Anyone knows why?
Thanks!