Clik here to view.
Compilation Errors for UVM constructs using xcelium
Hi,I will shortyly tell the problem:The following code line :if(!$cast(tmp,rhs))`uvm_fatal(get_type_name().toupper(), "Type mismatch")...
View ArticleClik here to view.
Set -access +rw for regression
I have an issue where forcing a value on a register works in simulator but not in regressionThis is how it is done in the...
View ArticleClik here to view.
How to do UVM transaction recording with irun?
Can anyone explain step-by-step how to record transactions in irun?e.g, what to do in UVM source code, which options for irun and etc.?
View ArticleClik here to view.
Code coverage for sv verification envrionment
I referred to the link below but it seems it is much a historical solution. Now I am trying on IES 15.023. So is it possible to generate code coverage for sv verification environment with...
View ArticleClik here to view.
Sort facility in Transaction Strip Chart
Hi,The IES 15.20-s024 seems didn't support well on the sort facility in Transaction Strip Chart.E.g,and click on 'Time' label on the 1st column, all the rows will be sorted by pure numbers without...
View ArticleClik here to view.
How do I port a signal (reference data) from testbench to RTL module?
I run some encryption logic and wish to mirror some reference data from testbench to RTL module, exactly the opposite compared to what one would normally do to mirror existing singals from RTL to TB....
View ArticleClik here to view.
Analyse the Functional Coverage of list of failing test case.
Vmanager unlike IMC/ICCR automatically excludes the coverage data of the failing test case, and help us analyse the functionally correct hits in coverage.But we can leverage use of functional coverage...
View ArticleClik here to view.
How do I add a compiled .a library to SV + DPI-C cosimulation?
I use UVM+SV+HDL test environment, and an existing C application. I intend to to run a cosimulation. The C app is ANSI C, has existing make file but it calls an 3rd party .a library. And it generates...
View ArticleClik here to view.
Possible to mix ncsim(64b) with DPI-C/C compiled in 32-bit address space?
I use ncsim 64 bit version 15.10, with DPI-C to run a large C application. The C does large amount of signal processing and mainly work in 32-bit environment. The ncsim uses 64 bit and I can't change...
View ArticleClik here to view.
How to collapse and expand the group in simvision with tcl command?
As far as I know, we can run group insert to insert signals as a group, but the group would be expanded by default.then how to insert the group as collapsed group with tcl command?Thanks.
View ArticleClik here to view.
How do I uncheck "Process statement" from sidebar in Simvision?
Hi Cadence, I use latest ncsim and run a large design. I use sidebar to quickly select signals and send to waveform. My VHDL design is so large that there are tens of "unnamed processes" and "process...
View ArticleClik here to view.
Cadence 17.2 Continuous Refresh problem
Running Windows 10 and having Pspice A/D simulation opened.The Capture CIS 17.2 keeps refreshing the buttons, without letting me work on anything.What should I do ?
View ArticleClik here to view.
code_coverage_Error_The_design_unit...
Hi All,I am doing code coverage, receiving following error;ncelab: 14.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.TOOL: ncelab 14.10-s014: Started on Jan 09, 2018 at 12:09:19 ISTncelab...
View ArticleClik here to view.
How to increase the signal name font size in Simvision?
I hope to find the font setting in 'Edit -> Preference -> General Options' , but it seems not there.Anyone can help on this?Thanks.
View ArticleClik here to view.
Efficiency of associative array
Hi,So far as I know, the associative array has better performance in searching items than SV queue.But in practice the improvement seems not as significant as expected when the index keep growing. E.g,...
View ArticleClik here to view.
How to get system time in SV?
Hi,I am familiar with $realtime that will return the simulation time in the test bench. But what if I want to get the system time? Is there any direct function call to achieve this?Thanks.
View ArticleClik here to view.
iprof_report_dir generated with only a hidden folder
Hi,After compiled the testbench with '-iprof' and run simulation for a while, I press 'Ctrl-C' to terminate the simulation. As usual there would be a folder named'prof_cpu' generated under...
View ArticleClik here to view.
C code generated by the veriloga
Is it possible to access the C code generated by the veriloga compiler?Thank you,Pietro
View ArticleClik here to view.
How to add hook when exit from simulation?
Hi,Is it possible to add hooks in UVM testbench or tools to dump some variables in ENV when the simulation is terminated by SIGINT like Ctrl-C?Thanks.
View ArticleClik here to view.
#ifdef #else #endif inside module instantiation in Verilog
Hi all, I am trying to reverse engineer an open source verilog code for learning purpose. The code has some similar structure as below(please ignore my syntax errors)...
View Article