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Configure clock frequency depends on operation mode- UVM
Hi everyoneI'm a newbie on UVM verification, I'm building a environment to verify my design. In my design It has a clock input whose the clock frequency can change from user. I intend to test the...
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DMS UVC Components
Good Morning.I would like to check who I can talk about the DMS UVC Components used for Mixed-Signal Verification.There are some Mixed-signal RAKs, examples inside the Cadence’s Verification Kit and...
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How to use cve_coverage_save_nc?
Hello,I'm trying to do functional verification using SystemC.I already create an structure using scv_coverpoint and scv_covergroup, and I can extract the coverage from covergroup using the function...
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e generation question
Hi,the next code used to work in IES 13.2 but results in error in 14.2.var idx : uint[0..7]; var num : byte = 0xA; gen idx keeping {read_only(num[it:it] == 0);};I am getting the next error...
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HAL lint check design_info file
Hi, I am trying to turn off some checking rules in the design_info file. I tried the example given by reference manualINFNOT {pattern = "*unused_*"} off;and it does not work. I also triedINFNOT...
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[HELP] Error on cosimulation of VHDL and SystemC with e testbench
Hello,I'm currently working in a project that I need to cosimulate two identical RTL DUTs in different HDLs (SystemC and VHDL) with a e testbench based on UVM. To do this I use irun to call necessary...
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UVM Monitor Help!!!
Hi all,I have a SPI interface, it has three modes to transfer the data out on IO[0:7]. In SPI standard there is just IO[0] is used. QPI mode, it uses IO[3:0] and In OPI mode, the whole IO are used....
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IFV connectivity Check failure debug
Hi, I am new to IFV and need your assistance in debugging one of the assertion failure.Scenario : assertion -add -interactive { (<path1>:top_scanb == 0) |-> ((<path2>:out_clk) ===...
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Controlling Seed to multi langauge verification environment
Hi I working on a multi language environment (UVM + C++)for an IP verification. I am new to C++. We are using a C++ model in our verification environment. We are precompiling the C++ model and call...
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Convergence Problem
Dear All,Right now, I am using a P channel MOSFET spice model from Toshiba "SSM3J15FU". Based on its datasheet test circuit i just tried to simulate the model.But i am getting the following error...
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Parameterized UVM Environment Creation Issue.
Hi all, when we are trying to create Parameterized UVM environment, we are not able to pass parameter from top to bottom of the component.Please help Us to solve this Issue, Our Dummy Environment...
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SystemC Verification float representation using integer constraints
I'm trying to generate constrained random float value using the IEEE 754 representation.I tried to represent the float values as a struct, such:struct my_float { uint sign; // it could be...
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VHDL sensitivity list checking in Incisive
Is it possible to perform checks for missing sensitivity list items when compiling VHDL using ncvhdl? I can't find anything in the manuals, although I may not be looking hard enough.Cheers,Dave
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debug when model violates the TLM 2.0 base protocol
Hello,How to debug when appear this message: "Warning: This model violates the TLM 2.0 base protocol. Performance analysis results may be wrong."?Thanks,Ciro Ceissler
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Forcing Verilog signal simple_port with pli_access == TRUE in Specman
Hi,I am working in Specman e and I am trying to force a signal value to a simple port that has its pli_access constrained to TRUE. I am unable to remove the pli_access constraint.If I use the force...
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Setting up simulation for UVM
Hi,I am trying run UVM environment using using INCISIV102-s040. When I run the irun command, seeing the below error.Compiling UVM package (uvm_pkg.sv) using uvmhome location <path>/uvm-1.1d/...
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Need help in Verilog file creation
I have a file which is extended to .tdf (Text Design File) from altera library. I want to convert it to traditional verilog code.Can anyone help in this regard?thanks,mahee
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How to make verilog function calls from non-DPI C model ?
Hello all,I am a software developer and new to design function verification.Currently I am designing C test program model to test hardware design via DPI. And we wish the test program be stopped until...
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Setting variable value from command line
Hi, I'm working on how to get the variable value set from command line and getting the value inside the class.If any body have some suggestions pls help in this regard?thanks,mahee
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Spectre processes sleep for random interval
I have a program which creates spectre simulation processes. It can do multiple simulations concurrently, however, even when running just one simulation, the spectre process will sleep a random...
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