Query regarding the usage of analog assertions in systemverilog file

Hi Team,

Presently I am developing a test-bench that include assertion checks for some analog signals. But facing some issues as described below.

1. I used the $cds_get_analog_value(hierarchy,"type") to get the value of an object in my design. The syntax I used is

someVar =  $cds_get_analog_value(hierarchy,"type");

But getting compilation error saying "Missing Right parentheses" and the = sign is highlighted in red.

I am not sure if some kind of special license is required to run simulation with the system tasks like $cds_get_analog_valure()/$cds_analog_is_valid() etc. Would someone please give me some clue on this? 

2. I used these system tasks in .sv file. Is it fine? Do I have to use file with extension .va/.vams? But the assert command is not being recognised  in .va/.vams file.

Thanks and Regards

Susanta