Transition model of the hardware design by Cadence IFV

Hello,

I wanted to know how the transition system of the hardware design is extracted from the Verilog code of the system by the Cadence IFV  tool. 

As far as I know,  model checking tools synthesize the RTL code written in Verilog or VHDL and then use model checking algorithms to perform verification against formal specifications. Does Cadence IFV follow the same process ?