Hi all,
Is it possible to place a pure VHDL and VHDL-AMS models of the same component inside the same cell?.
I would like to store all my models inside the project library, side by side with their schematic view. However, having different interfaces in the models (e.g. std_logic ports vs. electrical) means having different entities for the same component. I wonder if there is a way to reconcile this in the Virtuoso enviroment. DEFINE VIEW_MAP only works for Verilog(-AMS) based models.
In the VHDL in Design framework II guide (vhdlin) there is a brief comment about multiple entity/architecture pairs, but I believe this refers to instantiations of the same component inside a larger structural model.
Am I obliged to store pure VHDL and VHDL-AMS models in different libraries?
Thanks in advance.
Regards,
Lucho.