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Porting to new version getting stuck
I have ported my verification testbench from incisive 13.1 to 13.2.021 and getting stuck in simulation. Stimulation is stopping when it is detecting any interface (virtual) signal (say I want to drive...
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re: new version 14.10-s012 with assertions
Hi,i have written a simple assertion to check for 2 pulse asproperty(p1); @(posedge clk) ($rose(in1) ##1 $fell(in1)) |-> ##[1:$] ($rose(out1) ##1 $fell(out1));endpropertyAssuming at out1 is...
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vr_ad register coverage for multiple instances of the same kind
I have a vr_ad model set up which has lists of registers of the same kind. The automatic coverage gives coverage on a per-kind basis, so I know that one of the registers has been read/written, and that...
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Using Cadnece SMV model checker
Dear all,I was trying to download the SMV model checker from the website http://www.kenmcmil.com/smv.html. But, once I click the link given in the bottom of the page, its leading me to the main page...
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extend e language
Hello,Does anyone have another idea on how to extend a unit or struct by two value of a field at a time? (macro'less I would prefer, micro'with I already have a solution)type foo_t : [one, two,...
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Class definition outside module and package
Hi,I'm new to SV verfication and hence appreciate your help on this.Usually I've seen SV class definitions inside a module / package . I remember having read before that class definitions cannot exist...
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Back annotating the SDF data to a verilog nestlist in VHDL testbench
Dear expertsI am using VHDL as description language for my RTL development including testbenches and Cadence RC for synthesis. The synthesized netlist is in veilog and I would like to use it within the...
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Practical guide to integrate Specman with a ISS
Hello,I recently developed an Instruction Set Simulator using an Architecture Description Language called ArchC.My plan is to port this ISS into Cadence's tools for further Embedded Software...
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Understanding expression coverage
I have this piece of code: reg marker; always@(posedge clk or negedge rst_n) if ( ~rst_n ) marker <= 0; else if ( push_and_pushed ) if ( ( ( framecount==0 )...
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using sys.realtime
Hi, Can you please explain the influence of the `timescale and precision on sys.time and sys.realtime. In specman e language reference it says that:* "A field of type real named sys.realtime, which can...
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UVM_ML (SystemC + SystemVerilog TB)
Hi,Question about architecture of SystemC UVM + SystemVerilog UVM.Can those two approaches be mixed? 1. Can SystemC uvm_components exist within SystemVerilog's UVM tree hierarchy? In other words -...
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memory profile using simvision simulator
Hi ,Is there any way to check what portion of code takes what amount (or percentage ) of memory in simulation using simvision?I used "-profile" option which gives me the idea how many hits one type of...
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Post-layout simulation eval error
Hello All,I have designed a simple circuit and extracted the DSPF file. Now I am using the DSPF file as input to run po-layout simulation but I am confused for the measurement statements,in the DSPF...
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Broken Coverage Definition in VPLAN
HiI have a VPLAN, and I have a set of coverage data. I have mapped my functional coverpoints from the coverage data to the VPLAN.When I view the VPLAN (in eplanner) everything is mapped. When I view...
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ncsim: *E,TRSRANGE: range constraint violation (signal update).
Hello,I am able to run the simulation without any problems on modelsim. The same testbench on ncsim gives me the error after the simulation starts and runs for about 5us.Can someone please help me with...
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$nc_force never raises an error in ncsim
Hello Everyone,I am using nc_force to raise the signals in my testbench. I am using a path which never exists like this:$nc_force("blablabala", 5.0, "verbose");This never raises an ever during...
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Redirect Spectre results to buffer
I have written a program which reads in a text formatted tran.tran Spectre results file, analyzes the results, then modifies component parameters within input.scs in attempt to improve circuit...
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Irun not accepted systemverilog macro
I try to define macro`define MY_MACRO(par1, par2 = 0)If i use irun version 08, in console outputs error:`define MY_MACRO(par1, par2=0) | ncvlog: *E,EXPRPP (trunk/testbench/include/test_macro.svh,6|27):...
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Bind interface UVM issue
Hi everyoneI use bind to connect to a internal interface defined on module top_tb:bind dut.wt_clock_mux_glitch_free wt_clock_mux_if...
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Looking for the values of UVM register model in the simulation
Hello all,I have implented UVM register model and trying to write to and read values from the register model. I would like to see the register model content in incisive ncsim simulation. I dont see a...
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