Hello,
I recently developed an Instruction Set Simulator using an Architecture Description Language called ArchC.
My plan is to port this ISS into Cadence's tools for further Embedded Software Verification.
It seems a good idea, however I'm facing serious problems to integrate the ISS with Specman.
I was wondering if is there a practical guide, or examples with an ISS written in SystemC?
I tried to use the IVB to create the project files, but it seems so complicated, I'm looking for a simple example
that uses an ISS in SystemC. (All the examples in the documentation either use Verilog or Host code Execution)
Thank you.