UVM_ML (SystemC + SystemVerilog TB)

Hi,

Question about architecture of SystemC UVM  + SystemVerilog UVM.
Can those two approaches be mixed?

1. Can SystemC uvm_components exist within SystemVerilog's UVM tree hierarchy?
  In other words - can SystemVerilog instantiate SystemC class in itself?

2. If SystemVerilog UVM cannot instantiate in itself UVM components of SYstemC - it will mean that the testbench will have multiple tops (one top for SC, the other for SV), is it correct?

Many thanks

Witold Kaczurba