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simvision plugins - tcl tk 8.5? tcl 8.4 tile? c++ qt?
hi,is there a way to load Tcl Tk 8.5 when writing simvision plugins? is there a way to load the Tcl Tile package (or other Tcl GUI packages) in simvision?is there a c++ API for writing plugins (besides...
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ncverilog simulation verilog: error fmuk
Hi,I am trying to run a simulation on my schematic using NC-Verilog in Virtuoso. When I click simuate, I keep getting these errors:irun: *E,FMUK: The type of the file...
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IMC Coverage
Hi,i am working with imc coverage tool for ip coverage.certain if-elsif conditions are not covered even if i write various test patterns for it. even if i write all combinations in a testpattern for...
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cannot use $cds_analog_exists() or $cgav()
Hey all, do I need to use any special option in order to use the cadence system tasks to fetch values associated with analog objects (i.e., $cds_analog_exists() or $cgav() )? I'm using irun version...
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Forcing a VHDL signal from a Verilog Test/Env
I have a Testbench with a DUT which has VHDL and Verilog RTL modules. The tb_top is verilog. The test file is a verilog. From the verilog test, I need to force a signal inside the DUT several...
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Internal error during elabration phase
Hi,I am facing the below error when i tried to simulate a simple verilog environment,is this the tool setup issue w.r.t my source file or something other,please help me out. Writing initial simulation...
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How to save the signals in waveform window?
Hi, I'm a newbie in NC-verilog field.After launched the simvision, I sent some signals to waveform window from Design Browser window. Before I quit the simvision, how can I save the signals info in...
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Re: How to Simulate 64-bit VHDL Code in Cadence?
Hi shahein, this sounds like a VHDL issue and not a tool issue. Please refer to the VHDL LRM (IEEE1076) and refer to default types and precision. This will probably explain the behavior you are seeing...
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How to apply Dynamic Load and Reseed Methodology into UVM
I have found some application notes that provide guidance on how to use the Dynamic Load and Reseed Methodology with e/Specman. Is there an application note or other guidance on how to perform Dynamic...
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print all the `defines
Hi is there a way to print all the macros? we've got a sim env where macros are defined from command line, verilog and specman files. i am looking for a way to list all of the `define during...
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XBus XSoC XSerial examples
In INCISIV 10 and above where to find xbus,xsoc and xserial examples??
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tk plugin error in ncsim
Hi, Can anyone help us?We've already installed tk and tcl at '/usr/local/lib/tcl8.4' and '/usr/local/lib/tk8.4'. And 'libtk8.4.so' under /usr/local/lib/But, when trying to use tk in the simulator each...
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passing events as parameters to methods or TCM
Hi everyone, Is it possible to pass events to a method or TCM in e language? I have a TCM which emits events based on some register settings. I have five such registers and each...
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Looking for help with System Verilog in AMS
I've generated a netlist for a testcase and get the following error in the irun.log: Elaborating the design hierarchy:bias i_bias ( .ibias(ibias[3:0]), .vdd(vdd), .vss(vss), .en(en[0]));...
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Need help when using the AMS-Ultrasim tools,occuring some problems in...
Hi,When I use the Ultrsim tools verification the PLL Clock connect to digiatal module, the analog through the connect module(E2L) ，the output logic ignores some toogle edge,How to Solve this problem?
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SystemVerilog modport question
Hi All,I'm new to using interfaces and would like to implement an interface that connects a master module to 2 other identical slave modules. The interface simply contains a 2 bit data bus that is...
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Concatenating enumerated types in coverpoint
Hi,I will explain my query with an example. AddrHigh is a 16-bit address which is enumerated as NORMAL, DEVICE etc.. AddrLow is also a 16-bit address which is enumerated as TIMER, UART etc.. I want to...
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Specman Tutorial
Hi everybody ,Can anybody please suggest me quickstart tutorial to specman-e . I have knowledge of systemverilog uvm and now i want to shift to specman e. I Have specman 9.2 and above... are there any...
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CONFORMAL LEC-NON EQUIVALENT BLACK BOXES
Hi all,I'm very new to ASIC world.I have done lec b/w a RTL & a NETLIST.I have used hierarchial comparison for this.There are some un equivalent pointsI have got some few issues and doubts...
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comparing a signal length
Hi, I have a 1-bit signal whose low or high value needs to compared against a certain time value. For eg. signal x is high for more than 5ns at what places in the waveform. I could not use...
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