Quantcast
Channel: Cadence Functional Verification Forum
Viewing all articles
Browse latest Browse all 1074

SystemVerilog modport question

$
0
0

Hi All,

I'm new to using interfaces and would like to implement an interface that connects a master module to 2 other identical slave modules. The interface simply contains a 2 bit data bus that is driven by the master. I would like the interface to split the bus such that one slave is driven by the LSB and the other slave is driven by the MSB of the bus.

I believe the easiest way of doing this is to use modports - a master modport and a different modport for each slave. The interface code would then look something like this (modports are on single lines for compactness):

interface data_bus_if

logic [1:0] data;

modport master (output data);

modport slave0 (input .data_bit(data[0]));

modport slave1 (input .data_bit(data[1]));

endinterface : data_bus_if

I'd imagine this scenario is quite common but Incisive doesn't appear to support modport expressions. How can I implement the interface so that it compiles with Incisive?

Many thanks!


Viewing all articles
Browse latest Browse all 1074

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>