Clik here to view.
Any symbol for simulation of mutual induction between two inductors?
While placing parts, I cannot find a part which I can use to simulate 2 inductors in mutual induction with each other. Is anything similar there? I feel like this software was created with the idea of...
View ArticleClik here to view.
Generation of EVCD file for Verilog-AMS
Hi, Testbench developed in verilog-AMS and uses wreal as a ports and internal signals.When It's tried to generate EVCD for design ports with $dumpports() gives error related to "Wreal is not...
View ArticleClik here to view.
irun 11.10-s062 -R option and *W,WKWTLK "Waiting for a Exclusive lock"
My company recently upgraded from IUS 10.2 to 11.10. Our sim-regression suite uses the strategy of compiling a snapshot once (irun), then using that snapshot to run many different sim testcases in...
View ArticleClik here to view.
Use of a specify block within a SystemVerilog interface
Hi All, I'm currently converting a legacy testbench to use SystemVerilog interfaces between the DUT and some behavioural models. The testbench code includes a specify block that uses the $width system...
View ArticleClik here to view.
XBus XSoC XSerial examples
In INCISIV 10 and above where to find xbus,xsoc and xserial examples??
View ArticleClik here to view.
print all the `defines
Hi is there a way to print all the macros? we've got a sim env where macros are defined from command line, verilog and specman files. i am looking for a way to list all of the `define during...
View ArticleClik here to view.
list generation
Hi,I use the following code: var list : list of uint (bits:14); gen list keeping { it.size() == list_size_parameter; it.all_different(it); }; to gen a...
View ArticleClik here to view.
time between two events
Hi all is there any way by which i can measure time between two events (Specman e code)??e.g. time between two resets
View ArticleClik here to view.
Specman Tutorial
Hi everybody ,Can anybody please suggest me quickstart tutorial to specman-e . I have knowledge of systemverilog uvm and now i want to shift to specman e. I Have specman 9.2 and above... are there any...
View ArticleClik here to view.
How to match the UVC version & the cdn_e_utils version
Hi, When I try running the example tests from /vr_ahb/examples/sv/regular_env, I see the following during the start of simulation & simulator hangs giving a pop-up window. And in the terminal I see...
View ArticleClik here to view.
Switch to run through assertions
Sim Vision is halting my simulation when an assertion fires, is there a way to force the simulator to fire the assertion but continue running. I have tried this switch(-assert_logging_error_off) which...
View ArticleClik here to view.
Viewing dynamic objects in the Simvision waveform window
Hi All,I'm having trouble displaying the value of class data members in a Simvision waveform window (currently using version 12.10-s006).I'm using irun interactively to run my simulations, so I invoke...
View ArticleClik here to view.
irun: design.v is verilog and verilog AMS
Hi,We are migrating to an irun based flow to simplifiy our compile/elab/sim flow, and have a slight issue.We have a file design.v, containing module design. Depending on a define, this can either be a...
View ArticleClik here to view.
UNDERSTANDING CADENCE JTAG VIP DEMO
Hi ,I have run the JTAG VIP demo in sv lang . while running the demo the design browser shows : the top tb file , jtag if , sys hierarchy , packages and ovm top levels .1)what is the SYS hierarchy ?...
View ArticleClik here to view.
How to get the activity power in Simvision
Dear all, I'm using simvision to analysis activity power. Here is the command I used: read_vcd -vcd_module dut -module top -activity_profile -start_time 10000 -end_time 30000 -simvision...
View ArticleClik here to view.
How to Compile System Verilog
Hi,I use ncverilog: 05.70-s015: (c) Copyright 1995-2007 Cadence Design Systems, Inc.TOOL: ncverilog 05.70-s015: and foll switches -update +access+r +sv31aI egt the foll errsclass...
View ArticleClik here to view.
Package monitor_pkg could not be bound.
Hi I am using IES to compile system verilog classes and files:I am getting this error during compilation:cvlog: *E,NOPBIND (/proj/kunal/monitor_pkg.sv,10|28): Package monitor_pkg could not be...
View ArticleClik here to view.
electronics circuits opearation
is it possible to bring node voltage value as a resistor element value in pspice?justify.
View ArticleClik here to view.
Facing Error while running specman test
Hi,I am facing the below error when i run the specman test,please do let me know is this problem w.r.t environment variable settings. Compiler version D-2009.12-2_Full64; Runtime version...
View ArticleClik here to view.
View memory in NC-Verilog
Hi guys,I'm working on FPGA simulation.I want to see the data in memory unit (BlockRAM), could anyone tell me where I can find the memory view in NC-Verilog. Thanks.-Rohs
View Article