Re: How to Simulate 64-bit VHDL Code in Cadence?

 Hi shahein,

 this sounds like a VHDL issue and not a tool issue. Please refer to the VHDL LRM (IEEE1076) and refer to default types and precision. This will probably explain the behavior you are seeing and provide information on correct data types to use. Should you find any of the tools are not consistent with the LRM, please file a Service  Request so that it can be addressed

thanks,

gh-