Forcing a VHDL signal from a Verilog Test/Env

 I have a Testbench with a DUT which has VHDL and Verilog RTL modules.  The tb_top is verilog.  The test file is a verilog.  

 From the verilog test, I need to force a signal inside the DUT several hierarchies down.

 The signal I need to force is inside a VHDL module.   This signal is not available at the top level.

 How do I do it?

 I am using ncverilog/ncvhdl/irun version of 9.2.

 Any suggestions with some simple code example is going to be very helpful. 

 Thanks, 

 -Ashfaq Hossain