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ncelab ncutilities E,BUILDF
 Hi all, Switching from release 10 to 12.2, I've found some problem with testbench which uses nc utilities. ncelab (version 12.2) with option "-update" exit with  :...
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SimCompare - ignore time - compare only values
In SimCompare, is it possible to compare only the trace values and ignore the timestamps?For example, given the two traces of the same signal but at RTL and SystemCSystemC: 7@10ns , 10@20ns 10,...
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Cross coverage with ranges of a coverpoint
 HiI have a coverpoint with auto bins and I want to use this coverpoint ranges in a cross:   logic [3:0] out1_unmute_thr;  logic [0:0] 1l_ena;  logic [0:0] 1r_ena;  c_1l_ena : coverpoint 1l_ena;...
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Help on using VPWL_F_RE_FOREVER
Hi fellow designers! I get this error message while using the VPWL_F_RE_FOREVER. ERROR -- Invalid Time (.STIMULUS) in file "ordino_stims.stl" Line 13 I've spent hours browsing the PSpice Manual but...
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Missing module coverage
Hello,I am generating code coverage results for a design, but for some reason there are a couple of modules that are missing in the coverage report. I am using the imc tool to generate coverage, and...
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Simvision list view
Hi all,In simvision is there a way to display signals in a 'list view'?, that is, each row represent a time value at which a signal changed and each column is a signal.ThanksI.
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please help on verilog and vhdl combination problems
Hi Candence,I met a problem in using verilog and vhdl:1) I use verilog to make a testbench while the DUT all are made by VHDL2) I want to initialize the lower level memories in DUT. I have tried to use...
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How can I transfer a integer variable from verilog to VHDL?
Hi Candence: How can I transfer a integer variable from verilog to VHDL?As the code shows bellow:tb_top is verilog module;vhdl_top and bellows are vhdl module. module tb_top; integer...
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reinvoking from the tcl shell
Hello,I'd like to reinvoke the simulation using a tcl script. Is this possible? What's the tcl command to re-invoke the simulation? Actually, I would like a script that runs a preamble command to...
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Problem with GUI client on IES
 Hi allI have recently started to suffer from this problem, when trying to open debugger window or modules window etc...I am getting the next lines:# Trying to communicate with GUI client (timeout in...
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CMOS INVERTER LAYOUT DEBUG!?
 Hello all. So I am in the process of simulating my layout extraction. I ran DRC which was successful.I ran LVS which returned a negative output (my schematic netlist and extracted netlist DO NOT...
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interconnect check with PSL
Hi all, I want to check interconnectivity among several IP blocks(in VHDL and Verilog) with PSL vunits. However I have a problem in binding. As I understand, i can bind the vunit to only one entity....
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Different results for same netlist (in ADE-L & ADE-XL simulation)
Hello everybody,I encounter the problem of differences in the results of ADE-L and ADE-XL simulations from the Virtuoso schematic editor, although I checked the netlists of both simulations to be...
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Multiply number, USING ISTIM
(a) Hey I have a function in a netlist where I want to multiply two numbers as follows:.FUNC u() = a*b But here I will not get the multiplication as asterisk will cause the rest of the line to be...
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What is the desired phy response during LPI sendiing from GMAC to phy?
Hello sirI am sending LPI pattern from MAC to ethernet phy now I want to know that PHY is accepting my request and really goes into low power mode? because the pattern GMAC sends is correct but in...
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Importing C Function into System Verilog using DPI with 3-step process
Hi all, I want to import some C math function such as the sin and atan into my testbench using the DPI. It works fine when I use the "irum" command, the code should be right. But when I use the 3-step...
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Formal Verification
Please I'm beginner at Verification Field and shall anyone here recomment me to use formal verification and recommend me some materials. what about simulation based Methodology ,, is it better for me ?...
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Op-amp which can work at 100 kHz in PSpice
I am looking for an op-amp which can be used as a comparator at 100 kHz frequency. I am using uA741 and it works fine upto 10 kHz frequency but not beyond that. Could anyone please suggest an opamp...
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"No space left on device" Error!
I'm trying to simulate a design for 50 minutes but Simvision hangs up at ~ 10 minutes with the following error:Â error ncsim:Â *E, SST2ER:Â SST2 interface error:Â No space left on device.The design...
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EMGR, how to disable auto complemetary scan filter
How to disable default auto complemenary scan filter, like ius.tcl
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