IFV and IUS, what's the difference?
Hello Cadence,There are two similar simulation environment: IFV and IUS. Who know what's the difference with them? And one is another one's super set?Best regards,DavyOriginally posted in cdnusers.org...
View ArticleIFV run time errors
Hi,This is the first time I am using IFV tool. Whenever I try to run it it returns with the following errors:Error at line 1 of...
View Articledelay of the get_next_item method
Hi all I have some question regarding the delay of get_next_item method. Is there an option to get result from get_next_item in "zero time" (no delay at all).i have noticed that this method have an...
View ArticleAssertions, assume - Not supported
Hello,I've written few assertions in psl and have constrained them or asserted them in the tool.When I go to the source browser containing these, and choose Display values, I get Not Supported.Does...
View ArticleFSM_NoDeadlock - Explored (IFV)
Hello,I've been using the IFV tool for quite sometime now and I notice that when I run FSM assertions under AFA, No deadlock assertions remain explored while the others pass easily. Is there anyway to...
View ArticleWaveform in SimVision
Hi! I am debugging my simulation traces with SimVision (both signals and transactions). SimVision groups signal names in sets of three signals by alternating black and dark gray backgrounds. Sometimes...
View ArticleSimvision, the quickest way to know how many pulses one digital signal has?
Is there any why to know how may pulses one digital signal has between some time in waveform? I think simvision could support some way, like expression or calculation, to count how many rising or...
View ArticleZero-width pulse problem
I have a simulation that generate a zero-width pulse. There are two waveform file. One is vcd. Another one is shm. Both waveform was dump in same time. When i using Simvision to open both waveform, the...
View ArticleNot able to Merge Various coverage data base in ICCR tool.
Hi All,I have 10 coverage data base inside the cov_work/scope/ ,i am using the following script to merge,loading and generating the data base.merge -functional cov_work/scope/test * -output...
View ArticleVunits in PSL bind to spectre subckt
Hi,Can anybody share how they are binding a PSL vunit with the spectre subckt. Thanks
View ArticleCommand Line option for Local Pulse Filtering
Hi All, Goodmorning. I am trying to find out an option for filtering pulse local to a module.From docs, I see that, there are below command line options to filter pulse globally.-pulse_e, -pulse_r,...
View ArticleFormal Verification with SystemVerilog and ifv
Hi,i am trying to verify some SystemVerilogAssertions of a SV implementated communication network with incisif formal verifier, but the verification process takes a very long time and the computer...
View Articleprobe internal DUT signals
How to probe DUT(VHDL) internal signals for white box coverage??Regards,Pravin
View ArticleManaging "delta" delays with VHDL/PSL
Hi,We are using VHDL flavour PSL with a VHDL design, and are seeing assertion failures due to VHDL delta delays.I read that SystemVerilog has solved this problem by checking all assertions in a new...
View ArticleEnterprise Planner support system verilog / uvm ?
Does Enterprise planner supports importing of SV- UVM testbench? I am refering to Getting started document. It mentions of capability to import e testbench.Ref Incisive® Enterprise PlannerGetting...
View Articlewho can help me? who can give me a download sit of ius10.2 or 11.1 or 11.2
recently, i am study the uvm but i have no the ius soft ,who can help me appreciated. if u can give a download sit
View ArticleSV Help ! how can dump the wave from class ?
Hi, all Now I define a class ,and initiate it to a new class varible, I want to dump some signals from it , how can I get that ?
View Articleclocking...endclocking block question in the ifv
Hi, All I am a new beginner in the IFV, now I have a question of how to implement the clocking...endclocking in IFV. For the following code, I am intened to see the "din" in the waveform has a delay...
View Articlemultiple uvm_package defination error
Hi everybody, i have two different libraries named rtlwork and reggatwork and in both of them have an compiled UVM packages, one is used for normal rtl simulation and other is used for regression...
View Articlefiles required to use vams netlist
Hi All,I am new to mixed singal verifcation. I want to run mixed signal verifcation using irun. I grabbed the verilog modules and replace some of verilog modules with veriog A and some with cadence...
View Article