Hi Candence:
How can I transfer a integer variable from verilog to VHDL?
As the code shows bellow:
tb_top is verilog module;
vhdl_top and bellows are vhdl module.
module tb_top;
integer i;
$nc_force("tb_top.vhdl_top:ocmem:memarry[i]" , #data[i]);
endmodule
The ERROR message is:
expecting a integer index i.
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