please help on verilog and vhdl combination problems

Hi Candence,

I met a problem in using verilog and vhdl:

1) I use verilog to make a testbench while the DUT all are made by VHDL

2) I want to initialize the lower level memories in DUT. I have tried to use $nc_mirror, but it seems useless.

So would you like to give me some suggestions on how to initial memories in VHDL designs through  verilog testbench?

Thanks!