Hello all. So I am in the process of simulating my layout extraction. I ran DRC which was successful.I ran LVS which returned a negative output (my schematic netlist and extracted netlist DO NOT MATCH);however, I continued with the simulation hoping to see if I can gain some info from the plots...
Here is my layout and the plot of the simulation of the extraction (sorry for the bad quality layout image).
Please help me debug this issue. What should I be looking for?
Thank you.
