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i want to check these assume properties are correct
Hi,I wrote some of the assumptions in my fifo design and now the assertion passing in my design.Before assemptions that assert property was failing. assumptions are as below:///Assumtion to check...
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Specman plusargs
Hi,I would like to pass some parameters to my e testbench at run time. Does Specman have the nifty feature of plusargs (what SystemVerilog simulators have). A similar feature would also be...
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Stept through UVM code
Hi,I'm trying to step through the SV UVM library code, but I just can't manage. I tried the built in library in IUS and also a version downloaded from Accelera. Both setups have -linedebug on the...
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Multi Language Intergration:integrating system verilog over e
Hi all, i have to integrate sv wrapper over e... if we integrate by using tlm_nonblocking_put we are facing below error please any body have an idea to resolve this error... *** Error: Unsupported...
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e testflow
Hi,I am using e testflow, and encountering an interesting case that i would like to share and get your feedbacks.I have an environment "A" with tf_domain == domain_a.Under this environment i am...
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Is there any option like +ntb_random_seed in VCS for ncverilog?
I wonder how to generate random seed for simulation with ncverilog. Is there any option like +ntb_random_seed_automatic? Thanks!!
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One question about system verilog `__LINE__ define
There is a compiler derective in system verilog -- `__LINE__, it will expands to the current input line number. But I find it will return current line number -1. For example, in below code(the left is...
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How to manually flush display message buffer to console?
Hi,I have a few functions that take a long time to compute results. I'm trying to debug any performance problems. I know about the profiler and this has been of some use. No need to suggest this.I'd...
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Using variables within range repetition expression in e
Hi.I am facing some problems with using var in range repetition expression.I have the next code :a : unit;b : uint;keep b == a + 1234; event e1;event e2;expect {@e1;[a]*@clk} => @e2 ; // <==...
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UVM register Coverage collection
Hi i have a question regarding UVM registers coverage collection. The UVM register file is generated by the tool and by default in new function of the uvm register the coverage is OFF like below...
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Communication between Verilog BFM and C-Based Verification bench
HiI have a SOC verification bench in C/ASM and integrated SV/Verilog based BFM/VIP. The system level tests are based on C/ASM.To carry out functional simulations, the C/ASM tests are compiled, linked...
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How to disable vr_axi checks
Hi I am new to vr_axi enviorment,in my testbench i have some axi interfaces. I want to understand how to disable vr_axi checks like below"ERR_VR_AXI190***"
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How to disable automatically-generated cross bins?
Consider the following example code:(it's an example in SystemVerilog P1800-2009, Page 500) int i,j; covergroup ct; coverpoint i { bins i[ = { [0:1] }; } coverpoint j { bins j[ = { [0:1] }; } x1:...
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What's the difference between Incisive_Enterprise_Simulator and...
When I run RTL simulation by irun which is mainly composed of verilog and systemverilog code, sometimes it use Incisive_Enterprise_Simulator, sometimes it use Incisive_HDL_Simulator. So ,can someone...
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ICCR report generation issues for Multiple class instances
Hi , I create class entry_information which is extends from uvm_componemtin that entry_information class I have one cover_group entry_group which will be sampled for every posedge clk I created five...
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What's the difference between -seed and -svseed in irun?
There are two options to control random seed when using irun: -seed, -svseed.It seems that these two options is doing the same thing: set a random seed to RNG. And I tried many times, I can't find...
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passing IRUN command-line arguments into vsif file?
Hi,I use command-line arguments in my script and it looks like thisirun ... +define+MY_ARG ...I can run stand-alone simulation with different MY_ARG to different tests.How can I reuse my script in a...
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OS signal 11(segmentation violation)
Hi,I am getting OS signal 11 error and it is showing that I am using nested function in my code. What exactly the OS signal 11 error and why would we get this error. Please help me and thanks inadvance
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SystemC ncelab error
I'm trying to get a SystemC / Verilog simulation to run and am getting the following error messages:There is no information on any of the warning or error codes in Cadence help or on this site. Has...
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simvision : print window functionality
Hi ,I need to take a snapshot with a large number of signals.I tried using file > print window. this prints the waveform as a .ps/.eps file. when this is converted to jpeg/png/bmp and openedthe...
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